參數(shù)資料
型號: SY89844UMG TR
廠商: Micrel Inc
文件頁數(shù): 3/18頁
文件大?。?/td> 0K
描述: IC MUX LVDS RPE 2:1 PREC 24-MLF
標準包裝: 1,000
系列: SY89
類型: 多路復用器
電路: 1 x 2:1
獨立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應(yīng)商設(shè)備封裝: 24-MLF?(4x4)
包裝: 帶卷 (TR)
其它名稱: SY89844UMGTR
SY89844UMGTR-ND
Micrel, Inc.
SY89844U
May 2007
M9999-052207-B
hbwhelp@micrel.com or (408) 955-1690
11
Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur
either
following
Case
#2
or
Case
#3,
depending upon the last valid state at the CLK1.
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend on rise and fall time of the input signal and
on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
Timing Diagram 4
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