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參數(shù)資料
| 型號(hào)： | SY89843UMG |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX CML RPE 2:1 PREC 24-MLF |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | SY89 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 2:1 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，24-MLF? |
| 供應(yīng)商設(shè)備封裝： | 24-MLF?（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2097-5 SY89843UMG-ND |
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Micrel, Inc.
SY89843U
Oct. 1, 2013
8
M9999-052207-B
hbwhelp@micrel.com or (408) 955-1690
Functional Description
RPE MUX and Fail-Safe Input
The SY89843U is optimized for clock switchover
applications where switching from one clock to
another clock without runt pulses (short cycles) is
required. It features two unique circuits:
Runt-Pulse Eliminator (RPE) Circuit:
The RPE MUX provides a “glitchless” switchover
between two clocks and prevents any runt pulses
from occurring during the switchover transition. The
design of both clock inputs is identical (i.e., the
switchover sequence and protection is symmetrical
for both input pair, IN0 or IN1. Thus, either input pair
may be defined as the primary input). If not required,
the RPE function can be permanently disabled to
allow the switchover between inputs to occur
immediately. If the CAP pin is tied directly to VCC,
then the RPE function will be disabled and the
multiplexer will function as a normal multiplexer.
Fail-Safe Input (FSI) Circuit:
The FSI function provides protection against a
selected input pair that drops below the minimum
amplitude requirement. If the selected input pair
drops sufficiently below the 100mV minimum single-
ended
input
amplitude
limit
(VIN),
or
200mV
differentially (VDIFF_IN), then the output will latch to
the last valid clock state.
RPE and FSI Functionality
The basic operation of the RPE MUX and FSI
functionality is described with the following four case
descriptions. All descriptions are related to the true
inputs and outputs. The primary (or selected) clock
is called CLK1; the secondary (or alternate) clock is
called CLK2. Due to the totally asynchronous
relation of the IN and SEL signals and an additional
internal protection against metastability, the number
of pulses required for the operations described in
cases 1-4 can vary within certain limits. Refer to
“Timing Diagrams” for more detailed information.
Case #1 Two Normal Clocks and RPE Enabled
In this case, the frequency difference between the
two running clocks IN0 and IN1 must not be greater
than 1.5:1. For example, if the IN0 clock is 500MHz,
the IN1 clock must be within the range of 334MHz to
750MHz.
If the SEL input changes state to select the alternate
clock, then the switchover from CLK1 to CLK2 will
occur in three stages.
Stage 1: The output will continue to follow
CLK1 for a limited number of pulses.
Stage 2: The output will remain LOW for a
limited number of pulses of CLK2.
Stage 3: The output follows CLK2.
Timing Diagram 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89843UMG TR | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 Precision 2:1 LVPECL RPE & FSI MUX w/ 1:2 Fanout (I Temp, Green) RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY89843UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVPECL Runt Pulse Eliminator 2:1 |
| SY89844U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS Runt Pulse Eliminator 2:1 MUX with 1:2 Fanout and Internal Termination |
| SY89844U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Precision LVDS Runt Pulse Eliminator 2:1 |
| SY89844UMG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 2.5V 2:1 RPE/FSI LVDS MUX w/ 1:2 Fanout (I Temp, Green) RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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