hbwhelp@micrel.com or (408) 955-1690 Case #2 Input Cl" />
參數(shù)資料
型號(hào): SY89840UMG TR
廠商: Micrel Inc
文件頁(yè)數(shù): 15/15頁(yè)
文件大?。?/td> 0K
描述: IC MUX 2:1 LVPECL RPE/FSI 16MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: SY89
類(lèi)型: 多路復(fù)用器
電路: 1 x 2:1
獨(dú)立電路: 1
電壓電源: 單電源
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤(pán),16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 帶卷 (TR)
其它名稱(chēng): SY89840UMGTR
SY89840UMGTR-ND
Micrel, Inc.
SY89840U
Oct. 1, 2013
9
M9999-021705
hbwhelp@micrel.com or (408) 955-1690
Case #2 Input Clock Failure: Switching from a
selected clock stuck HIGH to a valid clock (RPE
enabled).
If CLK1 fails HIGH before the RPE MUX selects
CLK2 (using the SEL pin), the switchover will occur
in three stages.
Stage 1: The output will remain HIGH for a limited
number of pulses of CLK2.
Stage 2: The output will switch to LOW and then
remain LOW for a limited number of falling edges of
CLK2.
Stage 3: The output will follow CLK2
Timing Diagram 2
Note:
Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of
the CLK2 period.
Case #3 Input Clock Failure: Switching from a
selected clock stuck Low to a valid clock (RPE
enabled).
If CLK1 fails LOW before the RPE MUX selects
CLK2 (using the SEL pin), the switchover will occur
in two stages.
Stage 1: The output will remain LOW for a limited
number of falling edges of CLK2.
Stage 2: The output will follow CLK2.
Timing Diagram 3
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相關(guān)代理商/技術(shù)參數(shù)
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