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參數(shù)資料
| 型號： | SY89833ALMG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER TRANSLA 1:4 16-MLF |
| 產(chǎn)品培訓(xùn)模塊： | High Bandwidth Product Overview |
| 標準包裝： | 100 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVDS |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-3501-5 |
Micrel, Inc.
SY89833AL
Oct. 1, 2013
3
M9999-032609-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
15, 16
1, 2
3, 4
5, 6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
LVDS Differential Outputs: Normally terminated with 100
Ω across the pair (Q,
/Q). See “LVDS Outputs” section, Figure 2a. Unused outputs should be
terminated with a 100
Ω resistor across each pair.
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous
output enable. The synchronous enable ensures that enable/disable will only
occur when the outputs are in a logic LOW state. Note that this input is internally
connected to a 25k
Ω pull-up resistor and will default to logic HIGH state
(enabled) if left open.
9, 12
/IN, IN
Differential Input: This input pair is the differential signal input to the device.
Input accepts AC- or DC-Coupled differential signals as small as 100mV. Each
pin of the pair internally terminates to a VT pin through 50
Ω. Note that this input
will default to an intermediate state if left open. Please refer to the “Input
Interface Applications” section for more details.
10
VREF-AC
Reference Voltage: This output biases to VCC–1.4V. It is used when AC-
Coupling the input (IN, /IN). For AC-Coupled applications, connect VREF-AC to
VT pin and bypass with 0.1
μF low ESR capacitor to V
CC. See “Input Interface
Applications” section for more details. Maximum sink/source current is ±1.5mA.
Due to the limited drive capability, each VREF-AC pin is only intended to drive its
respective VT pin.
11
VT
Input Termination Center-Tap: Each side of the differential input pair terminates
to the VT pin. The VT pin provides a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
13
GND
Ground. GND pin and exposed pad must be connected to the most negative
potential of the device ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1
μF//0.01μF low ESR capacitors and
place as close to each VCC pin as possible.
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| SY89833ALMG TR | 功能描述:時鐘緩沖器 3.3V 1:4 PECL Fanout Buffer (I Temp, Green) RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SY89833ALMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Low Noise Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination |
| SY89833ALMI | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Low Noise Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination |
| SY89833ALMITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Low Noise Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination |
| SY89833L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 2GHz ANY-DIFFERENTIAL INPUT-TO-LVDS 1:4 FANOUT BUFFER/TRANSLATOR W/ INTERNAL TERMINATION |
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