Precision Edge SY89832U Micrel, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 August 2007 IN" />
參數(shù)資料
型號: SY89832UMG
廠商: Micrel Inc
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC CLK BUFFER TRANSLA 1:4 16-MLF
標準包裝: 100
系列: Precision Edge®
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2.5GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應(yīng)商設(shè)備封裝: 16-MLF?(3x3)
包裝: 管件
產(chǎn)品目錄頁面: 1083 (CN2011-ZH PDF)
其它名稱: 576-1432
2
Precision Edge
SY89832U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
August 2007
IN
/IN
EN
Q
/Q
0
11
0
1
01
1
0
X
0
0(1)
1(1)
Note 1. On next negative transition of the input signal (IN).
TRUTH TABLE
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89832UMG
QFN-16
Industrial 832U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
SY89832UMGTR(2)
QFN-16
Industrial 832U with Pb-Free
NiPdAu
bar line indicator
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Number
Pin Name
Pin Function
15, 16
Q0, /Q0
LVDS Differential (Outputs): Normally terminated with 100 across the pair (Q, /Q). See “LVDS
1, 2
Q1, /Q1
Outputs” section, Figure 2a. Unused outputs should be terminated with a 100 resistor across
3, 4
Q2, /Q2
each pair.
5, 6
Q3, /Q3
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default
to logic HIGH state (enabled) if left open.
9, 12
/IN, IN
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50. Note that these inputs will default to an intermediate state if
left open. Pleae refer to the “Input Interface Applications” section for more details.
10
VREF–AC
Reference Voltage: These outputs bias to VCC–1.4V. They are used when AC coupling the
inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with
0.01F low ESR capacitor to VCC. See “Input Interface Applications” section for more details.
Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin
is only intended to drive its respective VT pin.
11
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input
Interface Applications” section for more detaiils.
13
GND
Ground. GND pins and exposed pad must be connected to the most negative potential of the
device ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors and place as close to
each VCC pin as possible.
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
Q1
/Q1
Q2
/Q2
IN
VT
VREF-AC
/IN
/Q0
Q0
VCC
GND
Q3
/Q3
VCC
EN
16-Pin QFN
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