Precision Edge SY89828L Micrel, Inc. M9999-012208 hbwhelp@micrel.com or (408) 955-1690
參數(shù)資料
型號: SY89828LHG
廠商: Micrel Inc
文件頁數(shù): 12/13頁
文件大小: 0K
描述: IC CLK BUF MUX TRNSL 2:10 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復(fù)用器,變換器
電路數(shù): 2
比率 - 輸入:輸出: 2:10
差分 - 輸入:輸出: 是/是
輸入: LVDS,PECL
輸出: LVDS
頻率 - 最大: 1GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-EP-TQFP
包裝: 托盤
8
Precision Edge
SY89828L
Micrel, Inc.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Toggle Frequency
Note 2
1.0
GHz
tPHL
Differential Propagation Delay
LVPECL Input: 150mV
0.950
1.15
1.45
ns
tPLH
Note 3
LVPECL Input: 800mV
0.80
1.0
1.3
ns
LVDS Input: 100mV
1.10
1.35
1.60
ns
LVDS Input: 400mV
0.950
1.20
1.450
ns
tSWITCHOVER Clock Input Switchover
CLK_SEL to Valid Output
1.55
1.85
ns
tS(OE)
Output Enable Set-Up Time
Note 4
1.0
ns
tH(OE)
Output Enable Hold Time
Note 4
0.5
ns
tSKEW
Within Device Skew
Note 5
0°C to +85°C25
50
ps
–40°C35
75
ps
Part-to-Part Skew
Note 6
400
ps
tJITTER
Cycle-to-Cycle
Note 7
<1
ps
RMS
Total Jitter
Note 8
<1
2
ps
PP
tr, tf
Output Rise/Fall Times
200
290
400
ps
(20% to 80%)
Note 1.
100 termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane.
Note 2.
fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Outut swing is > 200mV.
Note 3.
Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
Note 4.
Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
Note 5.
The within-device skew is defined as the worst case difference between any two similar delay paths within a single device identical input transition,
operating at the same voltage and temperature.
Note 6.
The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage
and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
Note 7.
Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn –Tn+1
where T is the time between rising edges of the output signal.
Note 8.
Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-
to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(NOTE 1)
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