Precision Edge SY89825U Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690
參數(shù)資料
型號: SY89825UHI
廠商: Micrel Inc
文件頁數(shù): 5/9頁
文件大小: 0K
描述: IC CLK BUF MUX TRNSL 2:22 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: Precision Edge®
類型: 扇出緩沖器(分配),多路復(fù)用器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 2:22
差分 - 輸入:輸出: 是/是
輸入: LVDS,LVPECL
輸出: LVPECL
頻率 - 最大: 2GHz
電源電壓: 2.37 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-EP-TQFP
包裝: 托盤
5
Precision Edge
SY89825U
Micrel, Inc.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
TA = –40°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
fMAX
Max Toggle Frequency(2)
2
——
2
——
2
——
GHz
tPHL
Propagation Delay
ns
tPLH
(Differential)(3)
LVPECL IN
0.600
1.2
0.600
0.900
1.2
0.600
1.2
LVDS IN
0.800
1.4
0.800
1.1
1.4
0.800
1.4
tSKEW
Within-Device Skew(4)
——
35
20
35
——
35
ps
Part-to-Part Skew(5)
100
200
100
200
100
200
ps
tS(OE)
OE Set-Up Time(6)
1.0
——
1.0
——
1.0
——
ns
tH(OE)
OE Hold Time(6)
0.5
——
0.5
——
0.5
——
ns
t
JITTER
Random Jitter(7)
——
1
——
1
——
1ps(RMS)
Cycle-to-Cylce Jitter(8)
——
1
——
1
——
1ps(RMS)
Total Jitter(9)
——
10
——
10
——
10
ps(PP)
tr
Output Rise/Fall Time
300
600
300
450
600
300
600
ps
tf
(20% – 80%)
t(switchover) Input Switchover
——
1.2
——
1.2
——
1.2
ns
CLK_SEL-to-valid output
Notes:
1. Outputs loaded with 50
to V
CC – 2V. Airflow ≥ 300lfpm.
2. f
MAX is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50 to VCC –2V.
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
7. Random jitter is measured using K28.7 pattern, measured at
≤ f
MAX.
8. Cycle-to-cycle definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output signal.
9. Total jitter definition: with an ideal clock input of frequency
≤ f
MAX, no more than one output edge in 10
20 output edges will d eviate by more than the
specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(1)
VCC = 2.37V to 3.6V, GND = 0V
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