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參數(shù)資料
| 型號： | SY89809LTH |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:9 32-TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVPECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 500MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2089 SY89809LTH-ND |
Micrel, Inc.
SY89809L
December 2009
3
M9999-121409-D
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Type
Pin Function
2, 3
HSTL_CLK,
/HSTL_CLK
HSTL Input
Differential input: This HSTL input can be selected by CLK_SEL. If it is not
used, it can be left floating. This produces a LOW at the output. If driven by an
HSTL driver, an external 50 to ground termination is required at the input.
5, 6
LVPECL_CLK,
/LVPECL_CLK
LVPECL
Input
Differential input: This LVPECL input can be selected by CLK_SEL. If it is not
used, it can be left floating. This produces a LOW at the output (internal 75k
pull-downs).
4
CLK_SEL
LVTTL Input
Selected HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.
11k pull-up.
8
OE
LVTTL Input
Single-ended input: This LVTTL input disables and enables the Q0-Q8 output
pairs. It is internally synchronized to prevent glitching of the Q0-Q8 output
pairs. It is internally connected to a 11k pull-up resistor and will default to a
logic HIGH state if left open.
31, 29, 27,
23, 21, 19,
15, 13, 11
Q0 – Q8
HSTL Output
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50 to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused
output pairs may be left floating.
30, 28, 26,
22, 20, 18,
14, 12, 10
/Q0 – /Q8
HSTL Output
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50 to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused
output pairs may be left floating.
1
VCCI
VCC Core
Power
Core VCC connected to 3.3V supply. Bypass with 0.1F in parallel with 0.01F
low ESR capacitors as close to VCCI pin as possible.
9, 16, 17,
24, 25, 32
VCCO
VCC Output
Power
Output Buffer VCC connected to 1.8V supply. Bypass with 0.1F in parallel
with 0.01F low ESR capacitors as close to VCCO pins as possible. All VCCO
pins should be connected together on the PCB.
7
GND
Ground
Ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89809LTH TR | 功能描述:時(shí)鐘緩沖器 500MHz 1:9 Diff. HSTL Fanout Buffer (Green) RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SY89809LTHTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER |
| SY898225UH | 制造商:Synergy 功能描述: |
| SY89823L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR |
| SY89823L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR |
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