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參數(shù)資料
| 型號(hào)： | SY89808LTI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUF MUX TRNSLA 2:9 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器，變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVPECL |
| 輸出： | HSTL |
| 頻率 - 最大： | 500MHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP |
| 包裝： | 托盤 |
4
Precision Edge
SY89808L
Micrel, Inc.
M9999-091405
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
V
CCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; All outputs are loaded with 50 to GND; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
V
OUT ≥ 450mV
500
——
MHz
t
pd
Propagation Delay
CLK-to-Q
Note 3
0.800
1.000
1.200
ns
SEL-to-Q
Note 3
0.800
1.200
1.700
ns
t
SKEW
Within-Device Skew
Note 4
——
25
ps
t
SKPP
Part-to-Part Skew
Note 5
——
400
ps
V
pp
Minimum Input Swing
Note 6
150
——
mV
LVPECL_CLK
V
CMR
Common Mode Range
Note 7
–1.5
—–0.4
V
LVPECL_CLK
t
S
OE Set-Up Time
Note 8
1.0
——
ns
t
H
OE Hold Time
0.5
——
ns
t
r, tf
Output Rise/Fall Time (20% – 80%)
250
450
650
ps
t
JITTER
Cycle-to-Cycle Jitter
Note 9
1ps
RMS
Total Jitter
Note 10
10
ps
PP
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
6. The V
PP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
7. V
CMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The
numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or
equal to V
PP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|.
8. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the
next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
9. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n–Tn–1 where T is the time between rising edges of the
output signal.
10. Total jitter definition: with an ideal clock source of
≤ f
max, no more than one output edge in 10
12 output edges will deviate by more than the
specified amount.
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