參數(shù)資料
型號(hào): SY89645LK4G TR
廠(chǎng)商: Micrel Inc
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFFER 1:4 650MHZ 20TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類(lèi)型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無(wú)/是
輸入: LVCMOS,LVTTL
輸出: LVDS
頻率 - 最大: 650MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱(chēng): SY89645LK4GTR
SY89645LK4GTR-ND
Micrel, Inc.
SY89645L
June 2011
3
M9999-060711
hbwhelp@micrel.com
Ordering Information
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
SY89645LK4G
K4-20-1
Industrial
SY89645LK4G with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY89645LK4GTR
(2)
K4-20-1
Industrial
SY89645LK4G with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2.
Tape and Reel.
Pin Configuration
20-Pin TSSOP (K4-20-1)
Pin Description
Pin Number
Pin Name
Pin Function
1, 9, 13
GND
Power Supply Ground.
2
CLK_EN
Clock Enable. When LOW, Q outputs are forced low, /Q outputs are forced high. The synchronous
nature of the enable function forces the output clocks to enable or disable following a rising and a
falling edge of the input clock. When HIGH, clock outputs follow input clock. Internal 50k pull-up
resistor. VTH = VCC/2. See “Clock Enable (CLK_EN) Description” section.
3, 5, 6, 7, 8
NC
No Connect.
4
CLKIN
LVCMOS/LVTTL Clock Input. This is the input to the device. Input accepts single-ended input signals
as small as 1.2V. VTH = VCC/2. Internal 50k pull-down resistor.
10, 18
VCC
Positive Supply Pins. Connect to 3.3V supply, bypass with low ESR capacitors, as close to pins as
possible.
11, 12
14, 15
16, 17
19, 20
/Q3, Q3
/Q2, Q2
/Q1, Q1
/Q0, Q0
LVDS Differential Output Pairs: Differential buffered copies of the input signal. The output swing is
typically 280mV. Normally terminated with 100 across the output pairs (Q and /Q). See “LVDS
Output Termination” section.
or (408) 955-1690
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