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參數(shù)資料
型號: SY89610LMG TR
廠商: Micrel Inc
文件頁數(shù): 3/17頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER PREC FREQ 32MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: Precision Edge®
類型: 頻率合成器
PLL:
輸入: CML,LVDS,LVPECL
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 694MHz
除法器/乘法器: 是/是
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 帶卷 (TR)
Micrel, Inc.
SY89610L
July 2008
11
M9999-071008-D
hbwhelp@micrel.com or (408) 955-1690
Functional Description
Overall Function
The SY89610L is designed to accept a high-jitter signal
and provide an ultra-low jitter and ultra-low phase noise
CML compatible clock signal. Unlike normal buffers, the
SY89610L is a jitter attenuator since it does not transfer
jitter across from input to output. This makes this
product an ideal solution for precision clock applications.
LC Voltage Control Oscillator (VCO)
The SY89610L uses an extremely low phase noise VCO
to prevent jitter at the output. At low frequencies, the
PLL produces more phase noise. To offset the noise,
the LC VCO provides an extremely low phase noise
signal that feeds to the output circuit. Unlike many
competitive VCOs, this VCO only requires a single
external component, which is a filter capacitor.
External Loop Filter Considerations
The SY89610L features an external PLL loop filter that
allows the user to tailor the PLLs behavior. It is
recommended that ceramic capacitors with NOP or X7R
dielectric be used because they have very low effective
series resistance. All other filter components are on-
chip. Internally, the filter has a resistor in series with the
external capacitor and a much smaller capacitor in
parallel with the series combination of the internal
resistor and external capacitor. The selectable PLL
bandwidths from 1kHz-to-10kHz allows the user to
select between different loop filter values. The external
capacitor must be placed as close to the device pins as
possible. While laying out the board, keep any supply or
signal traces lines away from the capacitor. Loop filter
capacitor layout should include a quiet ground plane
under the loop filter capacitor and loop filter pins.
Power Supply Filtering Techniques
As with any high-speed integrated circuit, power supply
filtering is very important. At a minimum, VDDA, VDD,
and all VDDO pins should be individually connected
using via to the power supply plane, and separate
bypass capacitors should be used for each pin. To
achieve optimal jitter performance, each power supply
pin should use separate instances of the circuit shown in
Power Supply Scheme below.
Power Supply Scheme
Jitter Generation
Jitter generation is the amount of jitter generated by the
part at the output when there is no jitter present at the
input clock. While the VCO and PLL are sources of jitter
in a synthesizer, the different loop bandwidth options aid
in reducing jitter. The SY89610L guarantees less than
2psRMS. See Jitter characteristics subsection.
Phase Noise
The SY89610L has very low phase noise at 1kHz offset
from the center frequency. Phase noise is measured at
the output with a jitter-free signal injected at the input.
The loop bandwidth settings have a minor impact on the
phase noise values. For 10kHz loop bandwidth, we
guarantee the phase noise less than -80dBc/Hz. See
Phase Noise curve.
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