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參數(shù)資料
| 型號： | SY89538LHG |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH/BUFF LVPECL/LVDS 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘合成器/扇出緩沖器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-EP-TQFP |
| 包裝： | 托盤 |
| 其它名稱： | 576-3240 SY89538LHG-ND |
Micrel, Inc.
SY89538L
January 2008
M9999-010808-E
hbwhelp@micrel.com or (408) 955-1690
21
Output Bank and Frequency Control
There are five independently programmable output
frequency banks, four differential LVPECL output
banks and one differential LVDS output bank with
three output pairs. Each bank has frequency control
DSEL, SELx and Enx to generate different divider
ratios (see “LVPECL and LVDS Output Post-Divider
Frequency Select” Tables). It can be programmed for
pass-through, internal divided VCO clock divide-by-
/2, /8 or disable state. When disabled, the non-
inverted output goes to static LOW and the inverted
output goes to static HIGH.
Output Logic Characteristics
See “Output Termination Recommendations” for
proper termination. When LVPECL single-ended
output is desired, the unused complimentary output
should be terminated. Unused LVPECL output pairs
can be left floating. LVDS output pairs should be
terminated with 100 across the pair. In order to
minimize jitter and skew, unused LVDS output banks
and unused LVDS output pairs should be terminated
with 100 across each pair.
LVPECL Outputs:
Typical voltage swing is 800mV into 50.
Common mode voltage is VCCO–1.3V.
LVDS Outputs:
Typical voltage swing is 325mV into 100.
Common mode voltage is 1.2V.
Output Termination Recommendations
LVPECL
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing
which results in low EMI. LVPECL is ideal for driving
50-and-100-controlled
impedance
transmission
lines. There are several techniques for terminating the
LVPECL output: Single-ended termination, Parallel
Termination
Thevenin-Equivalent,
3-Resistor
Y-Termination, and AC-coupled termination.
Single-Ended LVPECL Termination
Unused output pairs may be left floating. Terminating
single-ended and unused outputs will enhance the
performance. Terminate LVPECL outputs by 50 to
VCC–2V. The unused input terminal must be biased to
VCC–1.3V using a resistor network. See Figure 11h for
more details.
DC-Coupled LVPECL Parallel Termination
Terminate LVPECL by an output impedance of 50 to
VCC–2V. Termination resistor values are a function of
VCC. For a 3.3V supply, the optimal parallel
combination is 130||82. See Figure 12a for details.
The LVPECL output can also be terminated with three
50 resistors as shown in Figure 12b. A 0.1F low
ESR decoupling capacitor from VCC to Y-Junction is
recommended in order to reduce noise in the signal.
AC-Coupled LVPECL Termination
While terminating an AC-coupled LVPECL signal, pull-
down resistor is used to create a DC current path to
GND to produce an output swing. For 3.3V supply,
100 provides the necessary pull-down. At the final
destination, proper termination to create a VCC–1.3V
termination bias is required 82||130. Please refer
to Figure 12c.
Figure 12a. LVPECL Parallel Thevenin-Equivalent
Figure 12b. LVPECL Parallel Termination
Figure 12c. LVPECL AC-Coupled Parallel
Thevenin-Equivalent
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89538LHG TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY |
| SY89538LHH | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHH TR | 功能描述:IC SYNTHESIZR LVPECL/LVDS 64TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SY89538LHY | 功能描述:時(shí)鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Lead Free) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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