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參數(shù)資料
| 型號： | SY89537LMY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER/FANOUT BUFF 44MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-VFQFN 裸露焊盤，44-MLF? |
| 供應(yīng)商設(shè)備封裝： | 44-MLF?（7x7） |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY89537L
December 2007
M9999-121207-B
hbwhelp@micrel.com or (408) 955-1690
10
Functional Description
Overall Function
The
SY89537L
integrated
programmable
clock
synthesizer and fanout buffer is part of a precision
PLL-based clock generation family optimized for
internal system clock generation for (FPGAs, ASICs,
NPU) applications.
Input MUX
The device’s input patent-pending MUX accepts both
a single-ended or differential reference clock; and a
14MHz to 18MHz series resonant crystal (XTAL). The
input MUX has built-in isolation, which minimizes
crosstalk between the two inputs. The input MUX
drives the PLLs phase detector, which expects a
frequency between 14MHz and 18MHz, therefore, the
reference clock can be a maximum frequency of
144MHz when the reference divider is set to: divide-
by-8. The minimum frequency that the reference
accepts is 14MHz when the reference divider is set at:
divide-by-1.
PLL VCO
The VCOs range of operation is from 2.352GHz to
3.024GHz, and the output frequency range is from
73.5MHz to 756MHz. The minimum output frequency
is calculated according to the following equation:
r
PostDivide
der
OutoutDivi
PreDivider
vider
FeedbackDi
Divider
Pre
fphase
fOUT
×
=
8
2
84
2
14MHz
(min)
fOUT
×
=
73.5MHz
(min)
fOUT
=
The
maximum
output
frequency
is
calculated
according to the following equation:
1
2
84
2
18MHz
(max)
fOUT
×
=
756MHz
(max)
fOUT
=
Crystal Input and Oscillator Interface
The SY89537L features a fully integrated on-board
oscillator, which minimizes system implementation
cost. The oscillator is a series resonant, multi-vibrator
type crystal driver.
Oscillator Tips
1. Mount the crystal as close to the SY89537L
as possible to minimize parasitic effects.
2. Mount on the same plane as the SY89537 to
minimize on via hole inductance.
3. To minimize noise pick up on the loop filter
pins, cut the ground plane directly underneath
the loop filter component pads and traces.
4. Keep the crystal and its traces away from
adjacent noisy traces to minimize on noise
coupling.
Table 4 illustrates the crystal specifications. Figure 2
below illustrates how to interface the crystal with the
SY89537L.
Figure 2. Crystal Interface
Quartz Crystal Selection:
Note: Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron
External Loop Filter Considerations
The SY89537L features an external PLL loop filter
that allows the users to tailor the PLLs behavior. It is
recommended that ceramic capacitors with NPO or
X7R dielectric be used, since they have very low
effective series resistance. For applications that
require
ultra-low,
cycle-to-cycle
jitter,
use
the
components shown in Figure 3a. For best total jitter
and best spur reduction, use the components shown
in Figure 3b. Larger values of the pole capacitor (C2)
results in less total jitter; however, the loop stability
decreases. Loop stability decreases since the pole
capacitor begins to dominate over the zero capacitor
(C1). The external loop filter allows the user to change
the loop filter values for specific jitter requirements.
Using a smaller resistor in the loop filter decreases the
PLLs loop bandwidth. This results in less noise from
the PLL input, but potentially more noise from the
VCO.
Figure 3a. Loop Filter for Lowest
Cycle-to-Cycle Jitter
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