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參數(shù)資料
| 型號： | SY89537LMHTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 756 MHz, OTHER CLOCK GENERATOR, QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 819K |
| 代理商： | SY89537LMHTR |
Micrel, Inc.
SY89537L
July 2005
M9999-072105
hbwhelp@micrel.com or (408) 955-1690
8
AC Electrical Characteristics
VCCA = VCCD = +3.3V ±10%; VCCO = +2.5V ±5% or +3.3V ±10%, RL (LVDS) = 100 across the output, RL (LVPECL)
= 50 into VCCO–2V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
XTAL Input Frequency Range
Note 7
14
18
MHz
fIN
Reference Input Frequency Range
14
144
MHz
fPHASE
Phase Detector Operating Frequency Range
14
18
MHz
fOUT
Output Frequency Range
73.5
756
MHz
fVCO
Internal VCO Frequency Range
2352
3024
MHz
Note 8
15
50
ps
15
50
ps
tSKEW
LVPECL Output Banks (0–3), Bank-to-Bank
LVDS Output Banks (0–2), Bank-to-Bank
Part-to-Part Skew
Note 9
200
ps
tLOCK
PLL Lock Time
10
ms
Note 10
4
6
psRMS
Note 10
5
7
psRMS
Note 11
5.5
8
psPP
Note 12
80
100
psPP
Loop Filter Optimized for Cycle-to-Cycle Jitter
R = 130
C1 = 0.47F
C2 = 100pF
1-Sigma Cycle-to-Cycle Jitter (XTAL Reference)
1-Sigma Cycle-to-Cycle Jitter (RFCK Reference)
Deterministic Jitter
Total Jitter
Spur
-35
dBc@
fphase
tJITTER
XTAL/RFCK Crosstalk-Induced Jitter
Note 13
0.7
psRMS
BW
PLL Bandwidth
See “PLL Stability” Table
28.8
99.8
kHz
tDC
FOUT Duty Cycle
43
50
57
%
tr, tf
Output Rise/Fall Time (20% to 80%) LVPECL
100
250
400
ps
Output Rise/Fall Time (20% to 80%) LVDS
80
150
300
ps
tPW_SYNC_MIN
See “Synchronization”
8
Internal
clock
cycle
tPD_SYNC
See “Synchronization”
8
Internal
clock
cycle
Notes:
7.
Fundamental mode, series resonant crystal.
8.
The bank-to-bank skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
10. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23-1 PRBS pattern.
12. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 10
12 output edges will deviate by more
than the specified peak-to-peak jitter value.
13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89537LMY | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMY TR | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89538L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
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