hbwhelp@micrel.com or (408) 955-1690 5
參數(shù)資料
型號(hào): SY89537LMH
廠商: Micrel Inc
文件頁(yè)數(shù): 15/19頁(yè)
文件大小: 0K
描述: IC SYNTHESIZR LVPECL/LVDS 44-MLF
標(biāo)準(zhǔn)包裝: 260
系列: Precision Edge®
類型: 時(shí)鐘/頻率合成器
PLL:
輸入: CMOS,HSTL,LVDS,LVPECL,LVTTL,SSTL,晶體
輸出: LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 3:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 756MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-VFQFN 裸露焊盤,44-MLF?
供應(yīng)商設(shè)備封裝: 44-MLF?(7x7)
包裝: 管件
Micrel, Inc.
SY89537L
December 2007
M9999-121207-B
hbwhelp@micrel.com or (408) 955-1690
5
Pin Description (continued)
Input/Output
Pin Number
Pin Name
Pin Function
5, 6
RFCK, /RFCK
Reference Clock Differential Input. Input accepts any input, single-ended or differential:
TTL/CMOS, LVPECL, LVDS, HSTL, and SSTL. RFCK requires external termination.
See "Input Interface" section for details.
8, 9
XTAL2, XTAL1
Crystal Input. Directly connect a series resonant crystal across inputs. See “Quartz
Crystal Oscillator Specification” table. Place crystal as close to the input as possible,
keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and
place the XTAL on the same side as the SY89537L (component side).
12, 13
15, 16
34, 35
37, 38
POUT0, /POUT0
POUT1, /POUT1
POUT2, /POUT2
POUT3, /POUT3
100K LVPECL Output Drivers. Terminate all PECL outputs with 50 to VCCO-2V. Each
output pair has respective output frequency control (PSELx, PENx) pins. See "PECL
Output and Frequency Select Table" for proper coding. For low jitter applications, unused
PECL output pairs should be terminated with pull-down resistors. See "Output
Termination Recommendations" section for termination detail.
25, 26
28, 29
31, 32
LOUT0, /LOUT0
LOUT1, /LOUT1
LOUT2, /LOUT2
Differential LVDS Compatible Output Drivers. Output termination is 100 across the pair.
For low-jitter applications, unused LVDS output pairs should be terminated with 100
across the pair. See “Output Termination Recommendations” section for details.
Reference Input Driver Select Table
RSEL1
RSEL0
Internal Reference
Clock
0
RFCK / 8
0
1
RFCK / 4
1
0
RFCK / 2
1
RFCK / 1
Table 1. Reference Input Divider Select Table
Output and Frequency Select Tables
PSELx
PENx
POUTx
0
Disable Output
0
1
(VCO/4) / 2
1
0
(VCO/4) / 8
1
(VCO/4) / 1
Table 2. PECL Output and Frequency Select Table
LSEL
LEN
LOUTx
0
Disable Output
0
1
(VCO/4) / 2
1
0
(VCO/4) / 8
1
(VCO/4) / 1
Table 3. LVDS Output and Frequency Select Table
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