參數(shù)資料
型號(hào): SY89421VZC TR
廠商: Micrel Inc
文件頁(yè)數(shù): 3/8頁(yè)
文件大?。?/td> 0K
描述: IC PHASE LOCK LOOP 5/3.3V 20SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: ClockWorks™
類型: 鎖相環(huán)路(PLL)
PLL:
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.12GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 5.25 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC(寬型)
包裝: 帶卷 (TR)
其它名稱: SY89421VZCTR
SY89421VZCTR-ND
3
ClockWorks
SY89421V
Micrel
Pin
Function
I/O
F1
Filter Pin 1
I/O
F2
Filter Pin 2
I/O
RIN
Reference Input
I
RIN
Inverted Reference Input
I
FIN
Feedback Input
I
FIN
Inverted Feeback Input
I
HFIN
High Frequency Input
I
HFIN
Inverted High Frequency Input
I
HFOUT
High Frequency Output
O
HFOUT
Inverted High Frequency Output
O
FOUT
Frequency Output
O
FOUT
Inverted Frequency Output
O
VCC
VCCO
Output VCC
VEE
VEE (0V)
S1
Select Input 1 (TTL)
I
S2
Select Input 2 (TTL)
I
S3
Select Input 3 (TTL)
I
S4
Select Input 4 (TTL)
I
S5
Select Input 5 (TTL)
I
RIN, RIN
Reference frequency inputs. These are differential signal
pairs and may be driven differentially or single-ended.
FIN, FIN
Feedback frequency inputs. These are a differential signal
pair and may be driven differentially or single-ended.
HFIN, HFIN
High frequency feedback inputs. These are a differential
signal pair. Differential drive is recommended.
F1, F2
These pins are connection points for the loop filter, which is to
be provided off-chip. F1 is the high impedance side, F2 is the
reference side. The loop filter should be a first order, low pass
with a DC block. The difference voltage on these pins will be
a dc level, which is controlled by the loop feedback and
determined by the required VCO frequency.
FOUT, FOUT
Frequency outputs for the loops. These are differential, positive
referenced, emitter-follower signals and must be terminated
off chip. Termination in 50 ohms is recommended.
HFOUT, HFOUT
High frequency output. These are a differential signal pair.
Termination in 50 ohms is recommended.
S1, S2, S3, S4, S5
These are the frequency select inputs, and are used to
configure the PLL. They are compatible with standard TTL
signal levels. See the Frequency Selection Table for details
of the logic.
VCC
This is the positive supply for the chip. It should be decoupled
and should present a very low impedance in order to assure
low-jitter operation.
VCCO
This is the positive supply for the output buffer. It is constrained
to be equal to or less than the value of VCC. It should be
decoupled and should present a very low impedance for low-
jitter.
VEE
This pin is the negative supply for the chip and is normally
connected to ground (0V).
PIN NAMES
PIN DESCRIPTION
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