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參數(shù)資料
| 型號(hào)： | EP1S10F484I6N |
| 廠商： | Altera |
| 文件頁數(shù)： | 52/864頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX FPGA 10K LE 484-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 20 |
| 系列： | Stratix® |
| LAB/CLB數(shù)： | 1057 |
| 邏輯元件/單元數(shù)： | 10570 |
| RAM 位總計(jì)： | 920448 |
| 輸入/輸出數(shù)： | 335 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA（23x23） |
Altera Corporation
2–121
July 2005
Stratix Device Handbook, Volume 1
Stratix Architecture
I/O pin has an individual slew-rate control, allowing you to specify the
slew rate on a pin-by-pin basis. The slew-rate control affects both the
rising and falling edges.
Bus Hold
Each Stratix device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its last-
driven state. Since the bus-hold feature holds the last-driven state of the
pin until the next input signal is present, an external pull-up or pull-down
resistor is not needed to hold a signal level when the bus is tri-stated.
Table 2–29 shows bus hold support for different pin types.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than VCCIO to prevent overdriving
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when using open-
drain outputs with the GTL+ I/O standard or when the I/O pin has been
configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 k
Ωto weakly pull the signal level to the last-driven state.
See the DC & Switching Characteristics chapter of the Stratix Device
Handbook, Volume 1 for the specific sustaining current driven through this
resistor and overdrive current used to identify the next-driven input
level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Table 2–29. Bus Hold Support
Pin Type
Bus Hold
I/O pins
v
CLK[15..0]
CLK[0,1,2,3,8,9,10,11]
FCLK
v
FPLL[7..10]CLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1S10F672C6 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I 1057 LABs 345 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1S10F672C6N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I 1057 LABs 345 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1S10F672C7 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I 1057 LABs 345 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1S10F672C7N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I 1057 LABs 345 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1S10F672I7 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I 1057 LABs 345 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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