參數(shù)資料
型號: SY89420VJC TR
廠商: Micrel Inc
文件頁數(shù): 3/8頁
文件大?。?/td> 0K
描述: IC PHASE LOCK LOOP 5/3.3V 28PLCC
標準包裝: 750
系列: ClockWorks™
類型: 鎖相環(huán)路(PLL)
PLL:
輸入: PECL,TTL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.12GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 5.25 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應商設備封裝: 28-PLCC
包裝: 帶卷 (TR)
其它名稱: SY89420VJCTR
SY89420VJCTR-ND
3
ClockWorks
SY89420V
Micrel
PIN DESCRIPTION
RINA, RINA, RINB, RINB
Reference frequency inputs for loop A and B. These are
differential signal pairs and may be driven differentially or
single-ended.
FINA, FINA, FINB, FINB
Feedback frequency inputs for loop A and B. These are
differential signal pairs and may be driven differentially or
single-ended.
VBB, VTH
These are the reference voltages for use as bias for the
frequency inputs. The references are generated on-chip. VBB
is PECL compatible, while VTH is TTL compatible.
F1A, F2A, F1B, F2B
These pins are connection points for the loop filters, which are
to be provided off-chip. F1X is the high impedance side, F2X
is the reference side. The loop filter should be a first order, low
pass with a DC block. The difference voltage on these pins will
be a DC level, which is controlled by the loop feedback and
determined by the required VCO frequency.
FOUTA, FOUTA, FOUTB, FOUTB
Frequency outputs for the loops.
These are differential,
positive referenced, emitter-follower signals and must be
terminated off-chip. Termination in 50 ohms is recommended.
S1A, S2A, S1B, S2B, S3B, S4B
These inputs are used to select the configuration for PLLA and
PLLB. They are compatible with standard TTL signal levels.
See the Frequency Selection Table for details of the logic.
VCC
This is the positive supply for the entire chip excluding output
buffers.
It should be decoupled and present a very low
impedance in order to assure low-jitter operation.
VCCOA, VCCOB
These are the positive supplies for the output buffers. They
are constrained to be equal to the value of VCC. They should
be decoupled and present a very low impedance in order to
assure low-jitter operation.
VEE
This pin is the negative supply for the chip and is normally
connected to ground (0V).
C
=
1.0
F ±10% (X7R dielectric)
R
=
560
±10%
LOOP FILTER COMPONENT SELECTION
Pin
Function
I/O
F1A
Filter Pin 1A
I/O
F2A
Filter Pin 2A
I/O
RINA
Reference Input A
I
RINA
Inverted Reference Input A
I
FINA
Feedback Input A
I
FINA
Inverted Feedback Input A
I
FOUTA
Frequency Output A
O
FOUTA
Inverted Frequency Output A
O
F1B
Filter Pin 1B
I/O
F2B
Filter Pin 2B
I/O
RINB
Reference Input B
I
RINB
Inverted Reference Input B
I
FINB
Feedback Input B
I
FINB
Inverted Feedback Input B
I
FOUTB
Frequency Output B
O
FOUTB
Inverted Frequency Output B
O
VCC
VCCOA
Output A VCC
VCCOB
Output B VCC
VEE
VEE (0V)
VBB
PECL Threshold Voltage
O
VTH
TTL Threshold Voltage
O
S1A
Select Input 1A (TTL)
I
S2A
Select Input 2A (TTL)
I
S1B
Select Input 1B (TTL)
I
S2B
Select Input 2B (TTL)
I
S3B
Select Input 3B (TTL)
I
S4B
Select Input 4B (TTL)
I
PIN NAMES
F2X
R
C
F1X
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