參數(shù)資料
型號: SY89323L
廠商: Micrel Semiconductor,Inc.
英文描述: 3.3V DUAL DIFFERENTIAL LVPECL TO LVTTL TRASLATOR
中文描述: 3.3V雙差分LVPECL給LVTTL TRASLATOR
文件頁數(shù): 4/5頁
文件大?。?/td> 38K
代理商: SY89323L
4
Precision Edge
SY89323L
Micrel
V
CC
= +3.3V
±
10%; C
L
= 20pF, T
A
=
40
o
C to +85
°
C, unless otherwise noted. All parameters guaranteed by design and characteriza-
tion.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
t
pd
t
skpp
t
skew++
t
skew
t
jitter
Maximum Input Frequency
Notes 1, 2
275
MHz
Propagation Delay
1.5
2.5
ns
Part-to-Part Skew
Notes 3
0.5
ns
Within-Device Skew
Notes 4
0.3
ns
Within-Device Skew
Notes 5
0.3
ns
Cycle-to-Cycle
Note 6
2
ps
rms
Total Jitter
Note 7
25
ps
pk-pk
t
r
t
f
Output Rise/Fall Time
1.0V to 2.0V
0.5
1.0
ns
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Frequency at which guaranteed for functionality. V
OH
and V
OL
levels are guaranteed at DC only.
The f
MAX
value is specified as the minimum guaranteed maximum frequency. Actual operational maximum frequency may be greater.
Device-to-Device Skew considering HIGH-to-HIGH transitions at common V
CC
level.
Within-Device Skew considering HIGH-to -HIGH transitions at common V
CC
level.
Within-Device Skew considering LOW-to-LOW transitions at common V
CC
level.
Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n
T
n
1
,where T is the time between rising edges of the
output signal.
Total jitter definition: with an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edge will deviate by more than
the specified peak-to-peak jitter value.
Note 7.
AC ELECTRICAL CHARACTERISTICS
INPUT INTERFACE APPLICATIONS
IN
+3.3V
V
CC
1.3V
+3.3V
1k
1.6k
Single-Ended Input
(Terminating unused input)
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