hbwhelp@micrel.com or (408) 955-1690 DC Electrical Char" />
參數(shù)資料
型號: SY89307VMI TR
廠商: Micrel Inc
文件頁數(shù): 5/5頁
文件大?。?/td> 0K
描述: IC RECEIVER DIFF 3.3V/5V 8-MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: SY89
邏輯類型: 差分接收器
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,8-MLF?
供應(yīng)商設(shè)備封裝: 8-MLF?(2x2)
包裝: 帶卷 (TR)
其它名稱: SY89307VMITR
SY89307VMITR-ND
Micrel, Inc.
SY89809AL
July 2010
5
M9999-070110
hbwhelp@micrel.com or (408) 955-1690
DC Electrical Characteristics
TA = 0°C to +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
LVCMOS/LVTTL
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current
–150
150
A
IIL
Input LOW Current
–300
300
A
AC Electrical Characteristics
(5)
TA = 0°C to +85°C, unless otherwise noted.
0
25°C
85°C
Symbol
Parameters
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
VOpp
Differential Output Voltage
FOUT < 100MHz
FOUT < 500MHz
FOUT < 750MHz
600
450
800
700
510
600
450
800
700
510
600
450
800
700
510
mV
tPLH
tPHL
Propagation Delay
(Differential Configuration)
LVPECL_CLK to Q
HSTL_CLK to Q
680
690
800
830
930
990
700
820
850
950
1000
780
790
920
950
1070
1110
ps
tSkew
Pin-to-Pin Skew
(6)
Part-to-Part Skew
(7)
15
100
25
200
15
100
25
200
15
100
25
200
ps
tJITTER
Random Clock Jitter ( RMS)
1.4
3
1.4
3
1.4
3
ps
VPP
Input Voltage Swing
(8)
LVPECL
HSTL
200
1900
200
1900
200
1900
mV
tS
OE Set-Up Time
(9)
0.5
ns
tH
OE Hold Time
0.5
ns
tr, tf
Output Rise/Fall Times
(20% to 80%)
Q, /Q
350
600
350
450
600
350
600
ps
Notes:
5.
Outputs loaded with 50 to ground. Airflow ≥ 500lfpm.
6.
The Pin-to-Pin skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
7.
The Part-to-Part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
8.
VPP is the Input Voltage swing required to maintain AC characteristics listed herein. It represents the input voltage swing for CLK or /CLK.
9.
OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next
clock cycle.
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