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參數(shù)資料
| 型號(hào)： | SY89230UMG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 4/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIVIDER LVPECL 16-MLF |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘除法器 |
| PLL： | 無(wú) |
| 輸入： | CML，LVDS，PECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.2GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
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Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.2
Signal Descriptions
4.2.1 Host Port Signals
The host port is used to manage and monitor the CobraNet interface. Electrical operation
and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this
Manual.
The host port can operate in two modes in order to accomodate Motorola or Intel style
interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.
4.2.2 Asynchronous Serial Port (UART Bridge) Signals
Level-shifting drive circuits are typically required between these signals and any external
connections.
Table 2-1: Host Port Signals
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
HDATA[7:0]
Host Data
In/Out
J1:A19,
A[17:11]
111, 112, 114,
115, 117, 118,
102, 121
Host port data.
HADDR[3:0]
Host Address
In
J1:A20,
A[10:8]
105, 106, 109,110
Host port address.
HRW
Host
Direction
In
J1:A4
107
Host port transfer direction (Motorola mode).
HRD
Host Read
In
J1:A4
107
Host Read (Intel mode).
HREQ
Host Request
Out
J1:A6
140
Host port data request.
HACK
Host Alert
Out
J1:A3
102
Host port interrupt request.
HDS
Host Strobe
In
J1:A5
103
Host port strobe (Motorola mode).
HWR
Host Write
In
J1:A5
103
Host Write (Intel mode).
HEN
Host Enable
In
J1:A7
104
Host Port Enable.
HCS
Select
In
J1:A7
104
Select (Intel mode).
Signal
Description
Direction
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Notes
UART_RXD
Asynchronous Serial
Receive Data
In
J1:A1
26
Pull-up to VCC if unused.
UART_TXD
Asynchronous Serial
Transmit Data
Out
J1:B1
25
UART_TX_OE
Transmit Drive Enable
Out
J1:A2
23
Enable transmit (active high) drive for
two wire multi-drop interface.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SY89231U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:1GHz Precision, LVPECL ±3, ±5 Clock Divider with Fail-Safe Input and Internal Termination |
| SY89231UMG | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89231UMG TR | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 Divide-by-3 and 5 LVDS Clock Divider with Internal Termination and FSI (3.2GHz) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY89231UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2GHz Precision, LVDS ÷3, ÷5 Clock Divider |
| SY89250V | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:ENHANCED DIFFERENTIAL RECEIVER |
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