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參數(shù)資料
| 型號(hào)： | SY89221UMG |
| 廠商： | MICREL INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 89221 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64 |
| 封裝： | LEAD FREE, TQFP-64 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 828K |
| 代理商： | SY89221UMG |
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Micrel, Inc.
SY89221U
September 2006
8
M9999-092906-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
(8)
VCC = +2.5V ±5% or 3.3V ±10%, TA = –40°C to +85°C, RL = 50 to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT ≥ 400mV
1.5
2.0
GHz
IN-to-Q
800
1250
1600
ps
CLK_SEL-to-Q
700
1000
1400
ps
tPD
Differential Propagation Delay
/MR(H-L)-to-Q
700
1000
1400
ps
tRR
Reset Recovery Time
/MR (L-H)-to-IN
300
ps
tPD
Tempco
Differential Propagation Delay
Temperature Coefficient
225
fs/°C
Within-Bank Skew
Within same fanout bank
(9, 10)
10
35
ps
Bank-to-Bank Skew
Same divide setting
(11)
15
40
ps
Bank-to-Bank Skew
Different divide setting
(11)
25
60
ps
tSKEW
Part-to-Part Skew
Note 12
400
ps
Random Jitter (RJ)
Note 13
1
psRMS
Total Jitter (TJ)
Note 14
10
psPP
tJITTER
Cycle-to-Cycle Jitter
Note 15
1
psRMS
tr, tf
Output Rise/Fall Time
(20% to 80%)
At full output swing
120
180
270
ps
Divide-by-2 or Divide-by-4
47
53
Divide-by-1, input > 1GHz
45
55
%
Duty Cycle
Divide-by-1, input < 1GHz
47
53
Notes:
8.
Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed
by design and characterization.
9.
Within-bank skew is the difference in propagation delays among the outputs within the same bank.
10. Skews within banks depend on the number of outputs. Within-bank skew decreases if the bank has lesser outputs.
11. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
between each bank, after MR is applied.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern.
14. Total jitter definition: with an ideal clock input frequency ≤ fMAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89222L | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:3.3V DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR |
| SY89222LMG TR | 功能描述:轉(zhuǎn)換 - 電壓電平 3.3V Ultrasmall Dual LVTTL-to-LVPECL Translator (I Temp, Green) RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SY89222LMGTR | 制造商:Micrel Inc 功能描述: |
| SY89222LMG-TR | 功能描述:Mixed Signal Translator Unidirectional 1 Circuit 2 Channel 8-MLF? (2x2) 制造商:microchip technology 系列:SY89 包裝:剪切帶（CT） 零件狀態(tài):有效 轉(zhuǎn)換器類(lèi)型:混合信號(hào) 通道類(lèi)型:單向 電路數(shù):1 每個(gè)電路的通道數(shù):2 電壓 - VCCA:- 電壓?- VCCB:- 輸入信號(hào):TTL 輸出信號(hào):PECL 輸出類(lèi)型:差分 數(shù)據(jù)速率:- 工作溫度:-40°C ~ 85°C（TA） 特性:- 安裝類(lèi)型:表面貼裝 封裝/外殼:8-VFDFN 裸露焊盤(pán)，8-MLF? 供應(yīng)商器件封裝:8-MLF?（2x2） 標(biāo)準(zhǔn)包裝:1 |
| SY89222LMI TR | 功能描述:IC TRANSLATOR DUAL 3.3V 8-MLF RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - 變換器 系列:SY89 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 邏輯功能:變換器，雙向 位數(shù):2 輸入類(lèi)型:CMOS 輸出類(lèi)型:CMOS 數(shù)據(jù)速率:16Mbps 通道數(shù):2 輸出/通道數(shù)目:1 差分 - 輸入:輸出:無(wú)/無(wú) 傳輸延遲（最大）:15ns 電源電壓:1.65 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:10-UFQFN 供應(yīng)商設(shè)備封裝:10-UTQFN（1.4x1.8） 包裝:管件 |
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