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| 型號： | SY89206VMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 0K |
| 描述： | IC RECEIVER/BUFFER 1GHZ 8-MLF |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SY89 |
| 邏輯類型： | 差分接收器 |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，8-MLF? |
| 供應(yīng)商設(shè)備封裝： | 8-MLF?（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1090 (CN2011-ZH PDF) |
| 其它名稱： | 576-2945-6 |
Micrel, Inc.
SY89468U
November 2008
M9999-110308-D
hbwhelp@micrel.com or (408) 955-1690
3
Pin Description
Pin Number
Pin Name
Pin Function
1, 16, 23, 33
41, 48, 58
VCC
Positive Power Supply: Bypass with 0.1F||0.01F low ESR capacitors as close to the VCC
pins as possible.
64, 63
62, 61
60, 59
57, 56
55, 54
53, 52
51, 50
47, 46
45, 44
43, 42
39, 38
37, 36
35, 34
31, 30
29, 28
27, 26
25, 24
22, 21
20, 19
18, 17
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Q12, /Q12
Q13, /Q13
Q14, /Q14
Q15, /Q15
Q16, /Q16
Q17, /Q17
Q18, /Q18
Q19, /Q19
Differential Output Pairs: The output swing is typically 325mV. Used and unused outputs
must be terminated with 100 across the pair (Q, /Q). These differential LVDS outputs are a
logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
4, 13
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low
ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface
Applications” subsection.
5, 12
VT0, VT1
Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin.
The VT pin provides a center-tap for each input (IN, /IN) to a termination network for
maximum interface flexibility. See “Input Interface Applications” subsection.
6, 7
10, 11
IN0, /IN0
IN1, /IN1
Differential Inputs: These input pairs are the differential signal inputs to the device. These
inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50. Each input has level shifting resistors of 3.72k to VCC.
This allows a wide input voltage range from VCC to GND. See Figure 3, Simplified
Differential Input Stage for details. Note that when these inputs are left in an open state, the
FSI feature will override this input state and provide a valid state at the output. See
“Functional Description” subsection.
2, 3, 14, 15,
32, 40, 49
GND,
Exposed Pad
Ground. Exposed pad must be connected to a ground plane that is the same potential as
the ground pins.
9
OE
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is
internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will
be enabled/disabled following a rising and a falling edge of the input clock. VTH = VCC/2.
8
SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will
default to logic HIGH state if left open. VTH = VCC/2.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
0
1
0
X
0
1
0
X
0
1
0
1
X
1
0
1
0
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