參數(shù)資料
型號: SY87729LHY
廠商: Micrel Inc
文件頁數(shù): 12/17頁
文件大小: 0K
描述: IC SYNTHESIZER FRACTION N 32TQFP
標準包裝: 250
系列: AnyClock®
類型: 分數(shù)合成器
PLL:
主要目的: 以太網(wǎng),光纖通道,SONET/SDH/ATM
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 365MHz
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-EPAD-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
配用: 576-1404-ND - BOARD EVAL N SY87729 EXPERIMENT
其它名稱: 576-2062
SY87729LHY-ND
Micrel, Inc.
SY87729L
July 2011
4
M9999-072111-G
hbwhelp@micrel.com
Pin Configuration
32-Pin ePad TQFP (H32-2)
Pin Description
Pin Number
Pin Name
Pin Function
1, 24
VCCA
Analog Supply Voltage.
2, 5,11, 12, 13,
15, 16, 19, 20,
23, 28, 29
NC
No Connection. These pins are to be left unconnected.
3, 4
REFCLK
±
Differential PECL Input. .
6
PROGCS
Program Interface Chip Select (TTL Input). This signal forms part of the MicroWire interface.
When active high, this signal permits the acquisition of serial data. A falling edge on this input
causes SY87729L to re-acquire lock to a new frequency, based on the program downloaded to it.
7
PROGDI
Program Interface Data In (TTL Input). One data bit is sampled on each rising edge of PRGSK,
while PROGCS is active high.
8
PROGSK
Program Interface Serial Clock (TTL Input). One bit of configuration data is read in each clock
cycle
9, 17
VCC
Supply Voltage.
10
GND
Ground.
14
LOCKED
Lock Output. This indicates proper operation of all the blocks in the clock synthesis chain. Logic
high indicates that SY87729L is generating the expected frequency at the CLKOUT± output.
Logic low indicates that one or more PLL in the clock synthesis chain has yet to achieve proper
lock.
18
VCCO
Output Supply Voltage.
21, 22
CLKOUT
±
Reference Clock Output. This is the synthesized clock generated from REFCLK±. It can be used
to supply a reference clock to a data recovery device, such as Micrel’s SY87721L.
25, 32
GNDA
Analog Ground.
26, 27
WRVCF
±
Wrapper Filter (Analog I/O). These pins connect to the output from the wrapper synthesizer
charge pump, as well as the input to the corresponding VCO. A filter network, as described
below, converts the charge pump current to a voltage, and adjusts loop bandwidth
30, 31
FNVCF
±
Fractional-N Filter (Analog I/O). These pins connect to the output from the fractional-N
synthesizer charge pump, as well as the input to the corresponding Voltage Controlled Oscillator
(VCO). A filter network, as described below, converts the charge pump current to a voltage, and
adjusts loop bandwidth
or (408) 955-1690
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