參數(shù)資料
型號: SY87729LHI
廠商: Micrel Inc
文件頁數(shù): 2/17頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER FRACT 3.3V 32TQFP
標準包裝: 250
系列: AnyClock®
類型: 分數(shù)合成器
PLL:
主要目的: 以太網,光纖通道,SONET/SDH/ATM
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 365MHz
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP 裸露焊盤
供應商設備封裝: 32-EPAD-TQFP
包裝: 托盤
配用: 576-1404-ND - BOARD EVAL N SY87729 EXPERIMENT
Micrel, Inc.
SY87729L
July 2011
10
M9999-072111-G
hbwhelp@micrel.com
Care should be exercised when selecting the value of P
(Table 1) so that the voltage-controlled oscillator (VCO)
of the fractional-N PLL is not driven out of range. The
following conditions must be met:
fVCO(min) < fREF × Fractional Division < fVCO(max)
or
or (408) 955-1690
)
fVCO(min) < fREF ×
(
+
±
P
Q
1
P
Q
1
P
Q
P
< fVCO(max)
where,
fVCO(min) = 540MHz
fVCO(max) = 729MHz
fREF = Frequency of the reference clock
DivSel3
DivSel2
DivSel1
DivSel0
P
0
17
0
1
18
0
1
0
19
0
1
20
0
1
0
21
0
1
0
1
22
0
1
0
23
0
1
24
1
0
25
1
0
1
26
1
0
1
0
27
1
0
1
28
1
0
29
1
0
1
30
1
0
31
1
32
Table 1. DivSel Divider Setting
Fractional-N Control
This circuit controls the P/P-1 divider, selecting the
appropriate divide ratio, either P or P-1, in the correct
pattern.
As explained in the example of Figure 2, controlling the
P/P-1 divider amounts to generating a repeating binary
bit stream. In that example, a “1” represents dividing by
4, and a “0” represents dividing by 3. The full cycle,
“101,” says to divide by 4 twice, and to divide by 3 once.
In the general case, the pattern “101” need not change
based on the P divider value. To multiply by 14/3 instead
of 11/3, for example, the same “101” pattern would be
used, but we would alternate dividing by 5 and 4, instead
of dividing by 4 and 3. The P value, in effect, represents
the integer part of the multiplication factor.
The repeating binary bit pattern really depends only on
the number of times to divide by P, and the number of
times to divide by P-1. We label the number of times to
divide by P as QP, and the number of times to divide by
P-1 as QP–1. The fractional-N synthesizer generates its
output frequency as per this formula:
fFNOUT =
±
+
±
1
P
Q
P
Q
1
P
Q
P
× fREF
In our figure two example, we multiply by 11/3, or 4 - 1/3.
Matching against the formula, P = 4, QP–1 = 1,
and QP = 2.
The SY87729L accepts QP and QP–1 values from its
MicroWire interface, where they exist as the 5-bit
values “qp” and “qpm1.” Both values are unsigned binary
numbers. QP and QP–1 are both constrained to be 31 or
less, and their sum is also constrained to be 31 or less.
That means that the denominator in the above formula
must be 31 or less.
As would be expected from the formula, setting QP to
zero causes frequency multiplication exactly by P-1.
Setting QP–1 to zero causes frequency multiplication
exactly by P. The SY87729L behavior is undefined if
both QP and QP–1 are both set to zero.
In the general case, the length of the repeating binary bit
pattern is QP + QP–1. It consists of QP “1”, and QP–1
“0.”
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