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參數(shù)資料
| 型號： | SY87701LHI |
| 廠商： | MICREL INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V 32-1250Mbps AnyRate⑩ CLOCK AND DATA RECOVERY |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 152K |
| 代理商： | SY87701LHI |
SY87701L
3
Micrel
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30
μ
s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY87701L contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will pull the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
RDOUTP, RDOUTN [Receive Data Output]
Differential
PECL.
These ECL 100K outputs represent the recovered data
from the input data stream (RDIN). This recovered data is
specified against the rising edge of RCLK.
RCLKP, RCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs represent the recovered clock
used to sample the recovered data (RDOUT).
TCLKP, TCLKN [Clock Output]
Differential PECL.
These ECL 100K outputs represent either the recovered
clock (CLKSEL = HIGH) used to sample the recovered data
(RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
External loop filter pins for the receiver PLL.
POWER & GROUND
V
CC
V
CCA
V
CCO
GND
NC
Supply Voltage
(1)
Analog Supply Voltage
(1)
Output Supply Voltage
(1)
Ground
No Connect
NOTE:
1. V
CC
, V
CCA
, V
CCO
must be the same value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY87701LHI-EVAL | 功能描述:BOARD EVAL SY87701 EXPERIMENT RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| SY87701LHITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs |
| SY87701LSI | 功能描述:IC CLOCK/DATA RECOVERY 32-TQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:AnyRate® 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| SY87701LZG | 功能描述:計(jì)時器和支持產(chǎn)品 3.3V Any-Rate 32-1250 Mbps CDR (I Temp, Green/28 Pin SOIC/Bulk) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SY87701LZG TR | 功能描述:計(jì)時器和支持產(chǎn)品 3.3V Any-Rate 32-1250 Mbps CDR (I Temp, Green/28 pin SOIC/T+R) RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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