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參數(shù)資料
| 型號(hào)： | SY84403BLMG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LIMIT CML 4.25GBPS 10-MLF |
| 特色產(chǎn)品： | SY84403BL Limiting Post Amplifier |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類(lèi)型： | 限制 |
| 電路數(shù)： | 1 |
| 輸出類(lèi)型： | 差分 |
| 電流 - 電源： | 41mA |
| 電流 - 輸出 / 通道： | 25mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-VFQFN 裸露焊盤(pán)，10-MLF? |
| 供應(yīng)商設(shè)備封裝： | 10-MLF? EP（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1089 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 576-3535-6 |
Micrel, Inc.
SY84403BL
May 2009
7
M9999-051509-A
hbwhelp@micrel.com or (408) 955-1690
Detailed Description
The SY84403BL low-power limiting post amplifier
operates from a single +3.3V power supply, over
temperatures from –40°C to +85°C. Signals with data
rates up to 4.25Gbps and as small as 10mVPP can be
amplified. Figure 1 shows the allowed input voltage
swing. The SY84403BL generates an LOS output,
allowing feedback to /EN for output stability. LOSLVL
sets the sensitivity of the input amplitude detection.
SY84403BL is available in the industry’s smallest form
factor, a tiny 10-pin (2mm x 2mm) MLF
package. It is
part of Micrel’s new family of ultra-small Fiber Optic
ICs.
Input Amplifier/Buffer
The SY84403BL’s inputs are internally terminated with
50
-to-REF. If not affected by this internal termination
scheme, upstream devices need to be AC-coupled to
the SY84403BL's inputs. Figure 2 shows a simplified
schematic of the input stage.
The high-sensitivity of the input amplifier allows
signals as small as 10mVPP to be detected and
amplified. The input amplifier allows input signals as
large as 1800mVPP. Input signals are linearly amplified
with a typically 38dB differential voltage gain. Since it
is a limiting amplifier, the SY84403BL outputs typically
800mVPP voltage-limited waveforms for input signals
that are greater than 20mVPP. Applications requiring
the SY84403BL to operate with high-gain should have
the upstream TIA placed as close as possible to the
SY84403BL’s
input
pins
to
ensure
the
best
performance of the device.
Output Buffer
The SY84403BL’s CML output buffer is designed to
drive 50
lines. The output buffer requires appropriate
termination for proper operation. An external 50
resistor to VCC or equivalent for each output pin
provides this. Figure 3 shows a simplified schematic
of the output stage and includes an appropriate
termination method. Of course, driving a downstream
device with a CML input that is internally terminated
with 50
-to-V
CC
eliminates the need for external
termination. As noted in the previous section, the
amplifier outputs typically 800mVPP waveforms across
25
total loads. The output buffer thus switches
typically 16mA tail-current. Figure 4 shows the power
supply current measurement, which excludes the
16mA tail-current.
Loss-of-Signal
The SY84403BL incorporates a chatter-free loss-of-
signal (LOS) open-collector TTL output with internal
4.75k
pull-up resistor as shown in Figure 5. LOS is
used to determine that the input amplitude is too small
to be considered a valid input. LOS asserts high if the
input amplitude falls below the threshold set by
LOSLVL and de-asserts low otherwise. LOS can be
fed back to the enable (/EN) input to maintain output
stability under a loss of signal condition. /EN de-
asserts low the true output signal without removing
the input signals. Typically, 3.5dB LOS hysteresis is
provided to prevent chattering.
Loss-of-Signal Level Set
A programmable loss-of-signal level set pin (LOSLVL)
sets the threshold of the input amplitude detection.
Connecting an external resistor between VCC and
LOSLVL sets the voltage at LOSLVL. This voltage
ranges from VCC to VREF. The external resistor creates
a voltage divider between VCC and VREF as shown in
Figure 6. If desired, an appropriate external voltage
may be applied rather than using a resistor. The
relationship between VLOSLVL and RLOSLVL is given by:
+
=
2.8
R
1.3
V
LOSLVL
CC
LOSLVL
where voltages are in volts and resistances are in k
.
The smaller the external resistor, implying a smaller
voltage difference from LOSLVL to VCC, lowers the
LOS sensitivity. Hence, larger input amplitude is
required
to
de-assert
LOS.
“Typical
Operating
Characteristics”
contains
graphs
showing
the
relationship between the input amplitude detection
sensitivity and RLOSLVL.
Hysteresis
The
SY84403BL
typically
provides
3.5dB
LOS
electrical hysteresis. By definition, a power ratio
measured in dB is 10log (power ratio). Power is
calculated as VIN
2/R for an electrical signal. Hence,
the same ratio can be stated as 20log (voltage ratio).
While in linear mode, the electrical voltage input
changes linearly with the optical power and hence the
ratios
change
linearly.
Therefore,
the
optical
hysteresis in dB is half the electrical hysteresis in dB
given in the datasheet. The SY84403BL provides
typically 1.75dB LOS optical hysteresis. As the
SY84403BL is an electrical device, this datasheet
refers to hysteresis in electrical terms. With 3.5dB
LOS hysteresis, a voltage factor of 1.5 is required to
de-assert LOS.
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