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參數(shù)資料
| 型號： | SY84113BUMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIMITING POST AMP 16-QFN |
| 標準包裝： | 1 |
| 類型： | 后置放大器 |
| 應(yīng)用： | 光纖學網(wǎng)絡(luò) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 標準包裝 |
| 其它名稱： | 576-3898-6 |
Micrel, Inc.
SY84113BU
January 2011
4
M9999-011711-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = 2.5 ± 5%; TA = –40°C to +85°C, typical values at VCC = 2.5V, TA = 25°C.; RLoad = 50 to VCC;
Symbol
Parameter
Condition
Min
Typ
Max
Units
tr, tf
Output Rise/Fall Time
(20% to 80%)
Note 4
150
260
ps
tJITTER
Deterministic
Random
Note 5
Note 6
15
5
psPP
psRMS
VID
Differential Input Voltage Swing
5
1800
mVPP
VOD
Differential Output Voltage
Swing
Note 4
700
800
950
mVPP
TOFF
LOS Release Time
Note 9
2
10
uS
TON
LOS Assert Time
Note 9
2
10
uS
LOSAL
Low LOS Assert Level
RLOSLVL = 10k, Note 7
3.9
mVPP
LOSDL
Low LOS De-assert Level
RLOSLVL = 10k, Note 7
5.6
mVPP
HYSL
Low LOS Hysteresis
RLOSLVL = 10k, Note 8
2
3.1
4.5
dB
LOSAM
Medium LOS Assert Level
RLOSLVL = 5k, Note 7
7
9.2
mVPP
LOSDM
Medium LOS De-assert Level
RLOSLVL = 5k, Note 7
13.6
16
mVPP
HYSM
Medium LOS Hysteresis
RLOSLVL = 5k, Note 8
2
3.4
4.5
dB
LOSAH
High LOS Assert Level
RLOSLVL = 100, Note 7
60
73
mVPP
LOSDH
High LOS De-assert Level
RLOSLVL = 100, Note 7
103
130
mVPP
HYSH
High LOS Hysteresis
RLOSLVL = 100, Note 8
2
3.0
4.5
dB
B-3dB
3dB Bandwidth
850
MHz
AV(Diff)
Differential Voltage Gain
38
dB
S21
Single-Ended Small-Signal Gain
26
32
dB
Notes
:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
ψJB uses a
4-layer and
θJA in still air unless otherwise stated.
4. Amplifier in limiting mode. Input is a 200MHz square wave.
5. Deterministic jitter measured using 1.250 Gbps K28.5 pattern, VID = 60mVPP.
6. Random jitter measured using 1.250Gbps K28.7 pattern, VID = 60mVPP.
7. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOSLVL for a particular LOS assert and its associated
de-assert amplitude.
8. This specification defines electrical hysteresis as 20log (LOS De-Assert/LOS Assert). The ratio between optical hysteresis and electrical
hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based on that
ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-4.5 dB, shown in the AC characteristics table, will be 1dB-3dB
Optical Hysteresis.
9. In real world applications, the LOS Release/Assert time can be strongly influenced by the RC time constant of the AC-coupling cap and the
50 input termination. To keep this time low, use a decoupling cap with the lowest value that is allowed by the data rate and the number of
consecutive identical bits in the application (typical values are in the range of 0.001F to 1.0F).
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