參數(shù)資料
型號(hào): SY58621LMG
廠商: MICREL INC
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback
中文描述: SPECIALTY TELECOM CIRCUIT, QCC24
封裝: 4 X 4 MM, LEAD FREE, MLF-24
文件頁(yè)數(shù): 5/19頁(yè)
文件大?。?/td> 308K
代理商: SY58621LMG
Micrel, Inc.
SY58621L
January 2006
5
M9999-012006-B
hbwhelp@micrel.com
or (408) 955-1690
Outputs
Pin Number
Pin Name
Pin Description
Loss-of-Signal Output. TTL-compatible output with internal 4.75k
Ω
pull-up resistor. Loss-of-
Signal asserts to logic HIGH when the receiver input amplitudes fall below the threshold set
by LOSLVL.
22
LOS
19
LOSLVL
RX Loss-of-Signal Level Set. A resistor (R
LOSLVL
) connected between LOSLVL and V
CC
sets
the threshold for the data input amplitude at which the LOS output is asserted. Default is max
sensitivity. LOSLVL is used to set the Loss-of-Signal (LOS) voltage. It is internally connected
to a 2.8k
Ω
pull-down resistor to an internal V
REF
voltage source. See “Typical Operating
Characteristics,” and “Application Implementation” sections for more details.
17, 16
RXQ, /RXQ
Receiver Differential Output. Output is CML compatible. Refer to the “Truth Table” and
“Output Stage” sections for more details. Unused output pair may be left open. The output is
designed to drive 400mV (800mV
PP
) into 50
Ω
to V
CC
or 100
Ω
across the pair.
5, 6
TXQ, /TXQ
Transmitter differential Variable Swing Output. Output is LVPECL-compatible. Please refer
to the “Truth Table” section for details. Unused output pair may be left open. Each output is
designed to drive 80mV (min) to 800mV (typ) into 50_ to V
CC
-2V depending on TXVCTRL.
Transmitter Output Reference Voltage. Output biases to V
CC
_
TXQ
-1.3V. Connecting V
REF_CTRL
to TXVCTRL sets the transmitter output swing to max swing.
Transmitter Input Reference Voltage. This output biases to V
CC
-1.3V. It is used when AC
coupling the transmitter input. For AC-coupled applications, connect TXVREF-AC to the
TXVT pin and bypass with a 0.01
μ
F low ESR capacitors to V
CC
. See “Input Stage” section for
more details. Maximum sink/source current is ±1.5mA.
8
VREF_CTRL
10
TXVREF-AC
Power Pins
Pin Number
Pin Name
GND,
Exposed Pad
Pin Description
3, 24
Ground. GND pins and exposed pad must be connected to the same ground plane.
12, 15, 18
VCC
3.3V ±10% Positive Power Supply. Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors and place
as close to each V
CC
pins as possible. Power pins are not connected internally and must be
connected to the same power supply externally.
21
VCC_RXIN
3.3V ±10% Receive Input Power Supply. Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors and
place as close to the V
CC_RXIN
pin as possible. Power pins are not connected internally and
must be connected to the same power supply externally.
4
VCC_TXQ
3.3V ±10% Output Transmit Power Supply. Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors
and place as close to the V
CC_TXQ
pin as possible. Power pins are not connected internally
and must be connected to the same power supply externally.
Truth Table
LOOPBACK
0
RXQ
RXIN
TXQ
TXIN
1
TXIN
RXIN
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