hbwhelp@micrel.com or (408) 955-1690 Ordering Infor" />
參數資料
型號: SY58608UMG TR
廠商: Micrel Inc
文件頁數: 3/10頁
文件大?。?/td> 0K
描述: IC CLOCK BUFFER 1:2 3GHZ 16-MLF
標準包裝: 1,000
系列: Precision Edge®
類型: 扇出緩沖器(分配)
電路數: 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 3GHz
電源電壓: 2.375 V ~ 2.635 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,16-MLF?
供應商設備封裝: 16-MLF?(3x3)
包裝: 帶卷 (TR)
其它名稱: SY58608UMGTR
SY58608UMGTR-ND
Micrel, Inc.
SY58608U
Oct. 1, 2013
2
M9999-102706-A
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58608UMG
QFN-16
Industrial
608U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58608UMGTR
(2)
QFN-16
Industrial
608U with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Inputs: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of
this pair internally terminates with 50 to the VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the outputs to its last valid state. See “Input Interface
Applications” section for more details.
2
VT
Input Termination Center-Tap: Each input terminates to this pin. The VT pin
provides a center-tap for each input (IN, /IN) to a termination network for maximum
interface flexibility. See “Input Interface Applications” section.
3
VREF-AC
Reference Voltage: This output bias to VCC–1.2V. It is used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” section for more details.
5, 8,13, 16
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to
the VCC pins as possible.
6, 7, 14, 15
GND,
Exposed pad
Ground. Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
9, 10
11, 12
/Q1, Q1
/Q0, Q0
LVDS Differential Output Pairs: Differential buffered output copy of the input signal.
The output swing is typically 325mV. Normally terminated 100 across the output
pairs (Q and /Q). See “LVDS Output Termination” section.
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