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參數(shù)資料
| 型號： | SY58607UMG TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER 1:2 3GHZ 16-MLF |
| 標準包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY58607UMGTR SY58607UMGTR-ND |
ICS843252-45
FEMTOCLOCKTM CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
8
ICS843252AG-45 REV. A OCTOBER 23, 2008
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
applications, R1
and R2 can be 100
. This can also be accomplished by removing
R1 and making R2 50
.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
XTAL_IN
XTAL_OUT
Ro
Rs
Zo = Ro + Rs
50
0.1f
R1
R2
VCC
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
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| SY58608UMG TR | IC CLOCK BUFFER 1:2 3GHZ 16-MLF |
| SY58609UMG TR | IC MUX 2:1 CML FSI INPUT 16-MLF |
| SY58610UMG | IC MUX 2:1 LVPECL FSI INP 16-MLF |
| SY58611UMG TR | IC MUX 2:1 LVDS FSI INPUT 16-MLF |
| SY58621LMG TR | TXRX 3.2GBPS CML/LVPECL 24-MLF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY58608U | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2Gbps Precision, 1:2 LVDS Fanout Buffer |
| SY58608U_10 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2Gbps Precision, 1:2 LVDS Fanout Buffer |
| SY58608UMG | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 4.25Gbps 2:1 LVPECL Multiplexer w/ FSI Inputs RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY58608UMG TR | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3.2Gbps 2:1 LVDS Multiplexer w/ FSI Inputs RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| SY58608UMGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input |
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