參數(shù)資料
型號: SY58605UMG TR
廠商: Micrel Inc
文件頁數(shù): 5/12頁
文件大?。?/td> 0K
描述: IC CLK BUFFER DVR 1:1 3GHZ 8-MLF
標準包裝: 1
系列: Precision Edge®
類型: 緩沖器/驅動器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 3GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,8-MLF?
供應商設備封裝: 8-MLF?(2x2)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1596-6
Micrel, Inc.
SY58605U
August 2007
2
M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Ordering Information
(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY58605UMG
DFN-8
Industrial
605 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
SY58605UMGTR
(2)
DFN-8
Industrial
605 with Pb-Free
bar-line indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
8-Pin DFN
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a
certain threshold (typically 30mV), them the Fail Safe Input (FSI) feature will
guarantee a stable output by latching the output to its last valid state. See “Input
Interface Applications” subsection for more details.
2
VT
Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides
a center-tap for each input (IN, /IN) to a termination network for maximum interface
flexibility. See “Input Interface Applications” subsection for more details.
3
VREF-AC
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling input
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection for more details.
5
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
6, 7
/Q, Q
LVDS Differential Output Pair: The output swing is typically 325mV. Normally
terminated with 100
across the pair (Q, /Q). See “LVDS Output Termination”
subsection for more details.
8
VCC
Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to
the VCC pin as possible.
相關PDF資料
PDF描述
SY58606UMG TR IC CLOCK BUFFER 1:2 3GHZ 16-MLF
SY58607UMG TR IC CLOCK BUFFER 1:2 3GHZ 16-MLF
SY58608UMG TR IC CLOCK BUFFER 1:2 3GHZ 16-MLF
SY58609UMG TR IC MUX 2:1 CML FSI INPUT 16-MLF
SY58610UMG IC MUX 2:1 LVPECL FSI INP 16-MLF
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