參數(shù)資料
型號(hào): SY58604UMG
廠商: MICREL INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 3.2Gbps Precision, LVPECL Buffer with Internal Termination and Fail Safe Input
中文描述: 58604 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC8
封裝: 2 X 2 MM, LEAD FREE, MLF-8
文件頁數(shù): 6/13頁
文件大?。?/td> 664K
代理商: SY58604UMG
Micrel, Inc.
SY58604U
Functional Description
September 2006
6
M9999-092606-A
hbwhelp@micrel.com
or (408) 955-1690
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mV
PK
(200mV
PP
), typically
30mV
PK
. Maximum frequency of SY58604U is limited
by the FSI function.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, then the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. Refer to “Typical
Characteristics” for detailed information.
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
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