V
參數(shù)資料
型號: SY58603UMG TR
廠商: Micrel Inc
文件頁數(shù): 5/8頁
文件大小: 0K
描述: IC CLK BUFFER DVR 1:1 3GHZ 8-MLF
標準包裝: 1
系列: Precision Edge®
類型: 緩沖器/驅動器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 3GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,8-MLF?
供應商設備封裝: 8-MLF?(2x2)
包裝: 標準包裝
產品目錄頁面: 1089 (CN2011-ZH PDF)
其它名稱: 576-1594-6
Micrel, Inc.
SY58603U
August 2007
5
M9999-082707-B
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = +2.5V ±5% or +3.3V ±10%, RL = 100
across the outputs, Input t
r/tf: <300ps; TA = –40°C to +85°C, unless
otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Frequency
NRZ Data
4.25
Gbps
VOUT > 200mV
Clock
2.5
3
GHz
tPD
Propagation Delay
IN-to-Q
VIN: 100mV-200mV
150
250
350
ps
VIN: 200mV-800mV
120
190
300
ps
tSkew
Part-to-Part Skew
Note 8
100
ps
tJitter
Data
Random Jitter
Note 9
1
psRMS
Deterministic Jitter
Note 10
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 11
1
psRMS
Total Jitter
Note 12
10
psPP
tr, tf
Output Rise/Fall Times
(20% to 80%)
At full output swing.
30
50
85
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
8.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
9.
Random jitter is measured with a K28.7 pattern, measured at
≤ f
MAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of
≤ f
MAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
相關PDF資料
PDF描述
SY58604UMG TR IC CLK BUFFER DVR 1:1 3GHZ 8-MLF
SY58605UMG TR IC CLK BUFFER DVR 1:1 3GHZ 8-MLF
SY58606UMG TR IC CLOCK BUFFER 1:2 3GHZ 16-MLF
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