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參數(shù)資料
| 型號： | SY58040UMY |
| 廠商： | MICREL INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | ULTRA PRECISION 4 X 4 CML SWITCH WITH INTERNAL I/O TERMINATION |
| 中文描述： | QUAD 4-CHANNEL, CROSS POINT SWITCH, QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MLF-44 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 120K |
| 代理商： | SY58040UMY |
3
SY58040U
Micrel
M9999-072904
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
Package
Type
MLF-44
MLF-44
MLF-44
Operating
Range
Industrial
Industrial
Industrial
Package
Marking
SY58040U
SY58040U
SY58040U
with
“
Y
”
designator
SY58040U
with
“
Y
”
designator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-free
SY58040U
SY58040UMI
SY58040UMITR
(2)
SY58040UMY
SY58040UMYTR
(2)
MLF-44
Industrial
Pb-free
Notes:
1.
Contact factory for die availability. Dice are guaranteed at T
A
= 25
°
C, DC
electricals only.
Tape and Reel.
2.
Pin Number
17, 15,
10, 8,
4, 2,
41, 39
16, 9,
3, 40
Pin Name
IN0, /IN0
IN1, /IN1
IN2, /IN2
IN3, /IN3
VT0, VT1
VT2, VT3
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept
AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin
through 50
. Note that these inputs will default to an indeterminate state if left open. Please refer to
the
“
Input Interface Applications
”
section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT
pins provide a center-tap to a termination network for maximum interface flexibility. See
“
Input
Interface Applications
”
section for more details.
Reference Voltage: This output biases to V
CC
–
1.2V. It is used when AC coupling the inputs.
Connect VRef-AC output pin to the VT input pin. Bypass each VRef-AC pin with a 0.01
μ
F low ESR
capacitor to V
CC
. See
“
Input Interface Applications
”
section for more details.
14,
11,
1,
42
18
19
38
37
5
7
VRef_AC0
VRef_AC1
VRef_AC2
VRef_AC3
SIN0
SIN1
SOUT0
SOUT1
CONF,
LOAD
These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs
are internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open.
These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs
are internally connected to a 25k
pullup resistor and will default to a logic HIGH state if left open.
These single-ended TTL/CMOS compatible inputs control the transfer of the addresses to the
internal multiplexers. See
“
Address Tables
”
and
“
Timing Diagram
”
sections for more details. Note
that these inputs are internally connected to a 25k
pull-up resistor and will default to a logic HIGH
state if left open.
Configuration Sequence
1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration.
2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration.
Buffer Mode
The SY58040U defaults to buffer mode (IN-to-Q) if the load and configuration control signals are
floating.
Differential Outputs: These CML output pairs are the outputs of the device. Please refer to the truth
table below for details. Unused output pairs may be left open. Each output is designed to drive
400mV into 100
across the pair, or 50
to V
CC
.
23, 24,
26, 27,
29, 30
32, 33
6, 22, 25,
28, 31, 34
12, 13, 20, 21,
35, 36, 43, 44 Exposed pad
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
VCC
Positive power supply. Bypass with 0.1
μ
F//0.01
μ
F low ESR capacitors and place as close to each
V
CC
pin.
Ground. GND and EPad must both be connected to most negative potential of chip ground.
GND,
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19
44 43 42 41 40 39 38 37
VREF_AC2
/IN2
VT2
IN2
CONFIG
VCC
LOAD
/IN1
VT1
IN1
/Q3
Q3
VCC
/Q2
Q2
VCC
/Q1
Q1
VCC
/Q0
Q0
V
I
V
G
G
/
S
S
V
/
V
G
G
I
S
S
20 2122
35
VREF_AC1
V
G
G
36
34
V
G
G
44-Pin MLF (MLF-44)
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