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參數(shù)資料
| 型號(hào)： | SY58026UMGTR |
| 廠商： | MICREL INC |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | ULTRA PRECISION DUAL 2:1 LVPECL MUX WITH INTERNAL TERMINATION |
| 中文描述： | 58026 SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MLF-32 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 655K |
| 代理商： | SY58026UMGTR |
5
Precision Edge
SY58026U
Micrel, Inc.
M9999-020207
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 2.5V
±
5% or 3.3V
±
10%; T
A
= –40
°
C to +85
°
C; R
L
= 50
to V
CC
–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
NRZ Data
Clock
5
Gbps
GHz
ps
ps
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
V
OUT
≥
400mV
V
IN
≥
300mV
6
t
pd
Propagation Delay
IN-to-Q
SEL-to-Q
160
100
230
220
7
8
310
400
15
20
100
1
10
1
10
t
SKEW
Input-to-Input Skew (Within-bank)
Bank-to-Bank Skew
Part-to-Part Skew
Data
Deterministic Jitter (DJ)
Clock
Cycle-to-Cycle Jitter (RJ)
Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
t
JITTER
Random Jitter (RJ)
Total Jitter (TJ)
Crosstalk-induced Jitter
Channel-to-Channel (Within-bank)
Output Rise/Fall Time 20% to 80%
Note 15,
Within-bank.
At full swing.
0.7
110
ps
RMS
ps
t
r
, t
f
35
70
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. V
IN
swing
≥
100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
23
–1 PRBS pattern
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
–T
n–1
where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency
≤
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
AC ELECTRICAL CHARACTERISTICS
(7)
TRUTH TABLES
INA0
0
1
X
X
/INA0
1
0
X
X
INA1
X
X
0
1
/INA1
X
X
1
0
SELA
0
0
1
1
QA
0
1
0
1
/QA
1
0
1
0
INB0
0
1
X
X
/INB0
1
0
X
X
INB1
X
X
0
1
/INB1
X
X
1
0
SELB
0
0
1
1
QB
0
1
0
1
/QB
1
0
1
0
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| SY58026UMITR | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:ULTRA PRECISION DUAL 2:1 LVPECL MUX WITH INTERNAL TERMINATION |
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| SY58027U_0708 | 制造商:MICREL 制造商全稱(chēng):Micrel Semiconductor 功能描述:ULTRA PRECISION DUAL 2:1 400mV LVPECL MUX WITH INTERNAL TERMINATION |
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