參數(shù)資料
型號(hào): SY56028XRMG
廠商: Micrel Inc
文件頁(yè)數(shù): 3/8頁(yè)
文件大小: 0K
描述: IC CLK BUFF MUX 4:2 4.5GHZ 32MLF
特色產(chǎn)品: SY56028XR Fanout Buffer
標(biāo)準(zhǔn)包裝: 60
系列: Precision Edge®
類(lèi)型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 4:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 4.5GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán),32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 管件
其它名稱(chēng): 576-3699-5
SY56028XRMG-ND
Micrel, Inc.
SY56028XR
April 2010
3
M9999-040810-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
1,3
5,7
25,27
29,31
IN0, /IN0
IN1, /IN1
IN2, /IN2
IN3, /IN3
Differential Inputs: Accepts differential signals as small as 200mV (400mVPP)
applied to the input of a 9, 18 or 27 inch 6mil FR4 stripline transmission line. See
“Input and Output Stage” section for details of this input.
2
6
26
30
VT0
VT1
VT2
VT3
Input Termination Center-Tap: Each side of the differential input pair terminates to
the VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC coupling, bypass VT with 0.1F low ESR capacitor to
VCC. See “Input Interface Applications” subsection and Figure 2a.
19
EQ
Three level input for equalization control.
15
18
SEL0
SEL1
Single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. This
input is internally connected to a 25k
pull-up resistor and will default to a logic
HIGH state if left open. Input logic threshold is VCC/2. See “Truth Table” for select
control.
16,17
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the VCC pin as possible. Supplies the input and core circuitry.
10,13,20,23
VCCO
Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO
pin as possible. Supplies the output buffers.
4,8,9,24,28,32
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
12,11
22,21
Q0, /Q0
Q1, /Q1
CML Differential Output Pair: Differential buffered copy of the input signal. The
output swing is typically 390mV. See “Functional Description” subsection for
termination information.
Truth Table
EQ Input
Equalization FR4 6mil
Stripline
LOW
9 “
FLOAT
18”
HIGH
27”
SEL1
SEL0
0
IN0 Input Selected
0
1
IN1 Input Selected
1
0
IN2 Input Selected
1
IN3 Input Selected
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