參數(shù)資料
型號: SY55859LMI TR
廠商: Micrel Inc
文件頁數(shù): 2/12頁
文件大?。?/td> 0K
描述: IC CROSSPOINT SWITCH DUAL 32MLF
標(biāo)準(zhǔn)包裝: 1,000
系列: SuperLite®
功能: 交叉點開關(guān)
電路: 2 x 2:2
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
電流 - 電源: 160mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,32-MLF?
供應(yīng)商設(shè)備封裝: 32-MLF?(5x5)
包裝: 帶卷 (TR)
其它名稱: SY55859LMITR
SY55859LMITR-ND
Micrel, Inc.
SY55859L
January 2010
10
M9999-012110-A
hbwhelp@micrel.com or (408) 955-1690
Application Information
The eight TTL compliant inputs to SY55859L are ENA0,
ENA1, ENB0 ENB1, SELA0, SELA1, SELB0 and
SELB1. These high impedance inputs do not default to a
stable logic state when left unconnected. Therefore,
these TTL compliant inputs cannot be left floating.
Connect these inputs to a valid control signal, or
hardwire to VCC or GND.
The four enable TTL inputs, when driven low, disable the
corresponding
output
stage.
This
reduces
power
consumption. Disabled output stages do not go into a
high impedance state. Rather, each pin of a disabled
output stage pair goes high through its respective 50
source termination.
The delay from a logic transition on an enable input to
the corresponding effect on the CML output is not
defined in the tables of this data sheet. This delay is 3ns
typical, and 10ns maximum. Please note that, for cases
where highly capacitive lines are being driven, the RC
effects of the line may make this delay longer.
The delay from a logic transition on a select input to the
corresponding CML output is also not defined in the
tables. It is 300psec typical, 500psec maximum.
For best performance, use good high frequency layout
techniques,
filter
VCC supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY55859L data inputs and outputs.
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