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參數資料
| 型號： | SY55855VKITR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL CML/PECL/LVPECL-to-LVDS TRANSLATOR |
| 中文描述： | DUAL PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO10 |
| 封裝： | MSOP-10 |
| 文件頁數： | 3/8頁 |
| 文件大?。?/td> | 88K |
| 代理商： | SY55855VKITR |
3
SuperLite
SY55855V
Micrel, Inc.
M9999-110705
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
V
CC
NC
X
/X
Figure 1. Hard Wiring a Logic “1”
(1)
NC
NC
V
CC
> 3.0V
X
/X
NC
V
CC
V
CC
≤
3.0V
X
/X
Figure 2. Hard Wiring a Logic “0”
(1)
Establishing Static Logic Inputs
The true pin of an input pair is internally biased to ground
through a 75k
resistor. The complement pin of an input
pair is internally biased halfway between V
CC
and ground
by a voltage divider consisting of two 75k
resistors. In this
way, unconnected inputs appear as logic zeros. To keep an
input at static logic zero at V
CC
> 3.0V, leave both inputs
unconnected. For V
CC
≤
3.0V, connect the complement input
to V
CC
and leave the true input unconnected. To make an
input static logic one, connect the true input to V
CC
, leave
the complement input unconnected. These are the only two
safe ways to cause inputs to be at a static value. In particular,
no input pin should be directly connected to ground. All NC
(no connect) pins should be unconnected.
Note 1.
X is either D0 or D1 input. /X is either /D0 or /D1 input.
Note 1.
X is either D0 or D1 input. /X is either /D0 or /D1 input.
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