參數(shù)資料
型號(hào): SY55855VKI
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: DUAL CML/PECL/LVPECL-to-LVDS TRANSLATOR
中文描述: DUAL PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO10
封裝: MSOP-10
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 83K
代理商: SY55855VKI
2
SuperLite
SY55855V
Micrel
PIN DESCRIPTIONS
D0, /D0 – CML/PECL/LVPECL Input (Differential)
This is one of the inputs. It is converted to LVDS onto
the Q0 and /Q0 outputs.
D1, /D1 – CML/PECL/LVPECL Input (Differential)
This is the other input. It is converted to LVDS onto the
Q1 and /Q1 outputs.
Q0, /Q0 – LVDS Output (Differential)
This is one LVDS output. It buffers the CML input that
appears at D0, /D0.
Q1, /Q1 – LVDS Output (Differential)
This is the other LVDS output. It buffers the CML input
that appears at D1, /D1.
FUNCTIONAL DESCRIPTION
V
CC
NC
X
/X
Figure 1. Hard Wiring a Logic “1”
(1)
NC
NC
V
CC
> 3.0V
X
/X
NC
V
CC
V
CC
3.0V
X
/X
Figure 2. Hard Wiring a Logic “0”
(1)
Establishing Static Logic Inputs
The true pin of an input pair is internally biased to ground
through a 75k
resistor. The complement pin of an input
pair is internally biased halfway between V
CC
and ground
by a voltage divider consisting of two 75k
resistors. In this
way, unconnected inputs appear as logic zeros. To keep an
input at static logic zero at V
CC
> 3.0V, leave both inputs
unconnected. For V
CC
3.0V, connect the complement input
to V
CC
and leave the true input unconnected. To make an
input static logic one, connect the true input to V
CC
, leave
the complement input unconnected. These are the only two
safe ways to cause inputs to be at a static value. In particular,
no input pin should be directly connected to ground. All NC
(no connect) pins should be unconnected.
Note 1.
X is either D0 or D1 input. /X is either /D0 or /D1 input.
D0
D1
Q0
/Q0
Q1
/Q1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
TRUTH TABLE
Note 1.
X is either D0 or D1 input. /X is either /D0 or /D1 input.
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