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參數(shù)資料
| 型號(hào)： | SY54011RMG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:2 3.2GHZ 16-MLF |
| 產(chǎn)品培訓(xùn)模塊： | High Bandwidth Product Overview |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | Precision Edge® |
| 類(lèi)型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML |
| 頻率 - 最大： | 3.2GHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán)，16-MLF? |
| 供應(yīng)商設(shè)備封裝： | 16-MLF?（3x3） |
| 包裝： | 帶卷 (TR) |
1
SY10E336
SY100E336
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
FEATURES
s 25
cutoff bus output
s Extended 100E VEE range of –4.2V to –5.5V
s 50
receiver output
s Transmit and receive registers
s 1500ps max. clock to bus
s 1000ps max. clock to Q
s Internal edge slow-down capacitors on bus outputs
s Additional package ground pins
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E336
s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E336 offer three bus transceivers with
both transmit and receive registers and are designed for
use in new, high-performance ECL systems. The bus
outputs (BUS0 - BUS2) are designed to drive a 25
bus.
The receive outputs (Q0 – Q2) are specified for 50
. The
bus outputs feature a normal logic HIGH level (VOH) and a
cutoff LOW level when at a logic LOW. At cutoff, the outputs
go to –2.0V and the output emitter-follower is “off”,
presenting a high impedance to the bus. The bus outputs
have edge slow-down capacitors.
The Transmit Enable pins (TEN) determine whether
current data is held in the transmit register or new data is
loaded from the A/B inputs. A logic LOW on both of the bus
enable inputs (BUSEN), when clocked through the register,
disables the bus outputs to –2.0V.
The receiver section clocks bus data into the receive
registers after gating with the Receive Enable (RXEN)
input.
All registers are clocked by rising edge of CLK1 or CLK2
(or both).
Additional grounding is provided through the ground
pins (GND) which should be connected to 0V. The GND
pins are not electrically connected to the chip.
3-BIT REGISTERED
BUS TRANSCEIVER
Pin
Function
A0–A2
Data Inputs A
B0–B2
Data Inputs B
TEN1, 2
Transmit Enable Inputs
RXEN
Receive Enable Input
BUSEN1, 2
Bus Enable Inputs
CLK1, 2
Clock Inputs
BUS0–BUS2
25
Cutoff Bus Outputs
Q0–Q2
Receive Data Outputs
VCCO
VCC to Output
PIN NAMES
SY10E336
SY100E336
Rev.: G
Amendment: /0
Issue Date:
March 2006
BLOCK DIAGRAM
0
1
DQ
D
Q
50
25
CUTOFF
0
1
DQ
D
Q
50
25
CUTOFF
0
1
DQ
D
Q
50
25
CUTOFF
Q0
BUS0
Q1
BUS1
Q2
BUS2
D
Q
A0
B0
A1
B1
A2
B2
TEN1
TEN2
BUSEN1
BUSEN2
CLK1
CLK2
RXEN
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