- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9779 > SY10EP16VZG TR (Micrel Inc)IC RCVR HS DIFF 3.3/5V 8SOIC PDF資料下載
參數(shù)資料
| 型號(hào)： | SY10EP16VZG TR |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR HS DIFF 3.3/5V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 10EP |
| 邏輯類型： | 差分接收器/驅(qū)動(dòng)器 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY89202U
August 2007
4
M9999-083107-C
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
2, 7, 8
DIVSEL1
DIVSEL2
DIVSEL3
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the three
banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2.
3, 6
IN, /IN
Differential Input: This input pair is the differential signal input to the device. This input accepts
AC- or DC-coupled signals as small as 100mV. The input pair internally terminates to a VT pin
through 50
. Note that these inputs will default to an indeterminate state if left open. Please
refer to the “Input Interface Applications” section for more details.
4
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
The VT pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section for more details.
5
VREF-AC
Reference Voltage: This output biases to VCC –1.2V. It is used for AC-coupling inputs IN and
/IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass with 0.01F
low ESR capacitor to VCC.
9
EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 – Q7 outputs. This
input is internally connected to a 25k
pull-up resistor and will default to logic HIGH state if left
open. The input-switching threshold is VCC/2. For the input enable and disable functional
description, refer to “Timing Diagram” section.
10, 19, 22, 31
VCC
Positive power supply. Bypass with 0.1F||0.01F low ESR capacitors as close to VCC pins
as possible.
16, 15, 14,
13, 12, 11
Q4, /Q4, Q5,
/Q5, Q6, /Q6
Bank 2 LVPECL differential output pairs controlled by DIVSEL2: LOW, Q4 – Q6 = ÷2, HIGH,
Q4 – Q6 = ÷4. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50
terminated at VCC–2V.
30, 29, 28,
27, 26, 25,
24, 23
Q0, /Q0, Q1,
/Q1, Q2, /Q2,
Q3, /Q3
Bank 1 LVPECL differential output pairs controlled by DIVSEL1: LOW, Q0 – Q3 = ÷1, HIGH,
Q0 – Q3 = ÷2. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50
terminated at VCC–2V.
18, 17
Q7, /Q7
Bank 3 LVPECL differential output pair controlled by DIVSEL3: LOW, Q7 = ÷2, HIGH, Q7 =
÷4. Unused output pairs may be left open. Each output is designed to drive 800mV into 50
terminated at VCC–2V.
32
/MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets
Q0 – Q7 outputs LOW and /Q0 – /Q7 outputs HIGH, and holds them in that state as long as
the /MR input remains LOW. This input is internally connected to a 25k
pull-up resistor and
will default to a logic HIGH state if left open. The input-switching threshold is VCC/2.
1, 20, 21
GND,
Exposed Pad
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Truth Table
/MR
( 1)
EN
( 2, 3)
DIVSEL1
DIVSEL2
DIVSEL3
Q0 – Q3
Q4 – Q6
Q7
0
X
0
1
0
X
0
1
0
1
2
1
2
4
Notes:
1. /MR asynchronously forces Q0 – Q7 LOW (/Q0 - /Q7 HIGH).
2. EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27484E8A35SA | CONN PLUG 6POS STRAIGHT W/SCKT |
| SY100EP16VKG TR | IC LN RCVR DIFF 3.3V/5V 8MSOP |
| MAX3232EEUP+G071 | TXRX RS-232 ESD PROTECT 20SSOP |
| SY100EP16UZG TR | IC LN RCVR DIFF 2.5V/3.3V 8SOIC |
| MAX3222EEUP+G071 | TXRX RS-232 ESD PROTECT 20TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY10EP16VZI | 功能描述:IC RCVR HS DIFF 5V/3.3V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:10EP 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY10EP16VZI TR | 功能描述:IC RCVR HS DIFF 5V/3.3V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:10EP 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY10EP31VKC | 功能描述:IC FLIP FLOP D 5V/3.3V 8-MSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:10EP 標(biāo)準(zhǔn)包裝:25 系列:74LS 功能:設(shè)置（預(yù)設(shè)）和復(fù)位 類型:JK 型 輸出類型:差分 元件數(shù):2 每個(gè)元件的位元數(shù):1 頻率 - 時(shí)鐘:25MHz 延遲時(shí)間 - 傳輸:20ns 觸發(fā)器類型:負(fù)邊沿 輸出電流高，低:400µA, 8mA 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 包裝:管件 其它名稱:74LS11274LS112AN74LS112NDM74LS112N |
| SY10EP31VKC TR | 功能描述:IC FLIP FLOP D 5V/3.3V 8-MSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:10EP 標(biāo)準(zhǔn)包裝:25 系列:74LS 功能:設(shè)置（預(yù)設(shè)）和復(fù)位 類型:JK 型 輸出類型:差分 元件數(shù):2 每個(gè)元件的位元數(shù):1 頻率 - 時(shí)鐘:25MHz 延遲時(shí)間 - 傳輸:20ns 觸發(fā)器類型:負(fù)邊沿 輸出電流高，低:400µA, 8mA 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 包裝:管件 其它名稱:74LS11274LS112AN74LS112NDM74LS112N |
| SY10EP31VKG | 功能描述:觸發(fā)器 3.3V/5V D Flip Flop with Set and Reset (I Temp, Green) RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。