參數(shù)資料
型號(hào): SY10E195JZ
廠商: Micrel Inc
文件頁數(shù): 1/8頁
文件大?。?/td> 0K
描述: IC DELAY LINE 128TAP 28-PLCC
標(biāo)準(zhǔn)包裝: 38
系列: 10E, Precision Edge®
標(biāo)片/步級(jí)數(shù): 128
功能: 可編程
延遲到第一抽頭: 1.39ns
接頭增量: 20ps
可用的總延遲: 1.39ns ~ 3.63ns
獨(dú)立延遲數(shù): 1
電源電壓: -4.2 V ~ -5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 管件
產(chǎn)品目錄頁面: 1086 (CN2011-ZH PDF)
其它名稱: 576-2501
SY10E195JZ-ND
1
Precison Edge
SY10E195
SY100E195
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Pin
Function
IN/IN
Signal Input
EN
Input Enable
D[0:7]
Mux Select Inputs
Q/Q
Signal Output
LEN
Latch Enable
SET MIN
Minimum Delay Set
SET MAX
Maximum Delay Set
CASCADE
Cascade Signal
DESCRIPTION
FEATURES
PIN NAMES
PROGRAMMABLE
DELAY CHIP
Precison Edge
SY10E195
SY100E195
s Up to 2ns delay range
s Extended 100E VEE range of –4.2V to –5.5V
s
20ps/digital step resolution
s >1GHz bandwidth
s On-chip cascade circuitry
s 75Kk
input pulldown resistor
s Fully compatible with Motorola MC10E/100E195
s Available in 28-pin PLCC package
The SY10/100E195 are programmable delay chips
(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.
The delay section consists of a chain of gates
organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195
with
a
digitally-selectable
resolution
of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.
Because the delay programmability of the E195 is
achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.
The E195 thus offers very fine resolution, at very high
frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
Rev.: H
Amendment: /0
Issue Date:
March 2006
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