參數(shù)資料
型號(hào): SY100EP14AUKG
廠商: Micrel Inc
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFF MUX 2:5 2GHZ 20TSSOP
標(biāo)準(zhǔn)包裝: 74
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
輸入: ECL,HSTL,LVPECL
輸出: ECL
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
其它名稱: 576-3697-5
SY100EP14AUKG-ND
7
SY88973V
Micrel, Inc.
M9999-110905
hbwhelp@micrel.com or (408) 955-1690
DETAILED DESCRIPTION
The SY88973V low-power, limiting post amplifier operates
from a single +3.3V
±10% or +5V ±10% power supply, over
an industrial temperature range of –40
°C to +85°C. Signals
with data rates up to 3.2Gbps and as small as 10mVPP can
be amplified. Figure 1 shows the allowed input voltage swing.
The SY88973V generates an LOS output, providing
feedback to /EN for output stability. LOSLVL sets the
sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88973V’s inputs are internally terminated with 50
to REF. Unless unaffected by this internal termination
scheme, upstream devices need to be AC-coupled to the
SY88973V’s inputs. Figure 2 shows a simplified schematic
of the input structure.
The high sensitivity of the input amplifier detects and
amplifies signals as small as 10mVPP. The input amplifier
allows input signals as large as 1800mVPP. Input signals
are linearly amplified with a typical 38dB differential voltage
gain. Since it is a limiting amplifier, the SY88973V outputs,
typically 800mVPP, voltage-limited waveforms for input
signals that are greater than 10mVPP. Applications requiring
the SY88973V to operate with high gain should have the
upstream TIA placed as close as possible to the SY88973V’s
input pins to ensure the device’s best performance.
Output Buffer
The SY88973V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to VCC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output structure and includes
an appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to VCC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs, typically 800mVPP, waveforms across 25
total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement which excludes the 16mA tail-current.
Loss-of-Signal
The SY88973V incorporates a chatter-free, LOS open-
collector TTL output with internal 4.75k
pull-up resistor as
shown in Figure 5. LOS is used to determine that the input
amplitude is too small to be considered a valid input. LOS
asserts high if the input amplitude falls below the threshold
set by LOSLVL and de-asserts low otherwise. LOS can be
fed back to the enable (/EN) input to maintain output stability
under a loss of signal condition. /EN de-assert low the true
output signal without removing the input signals. Typically
4.6dB LOS hysteresis is provided to prevent chattering.
Loss-of-Signal Level Set
A programmable, loss-of-signal level set pin sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and LOSLVL sets the voltage
at LOSLVL. This voltage ranges from V
CC to VREF. The
external resistor creates a voltage divider between VCC
and REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The relationship between VLOSLVL and RLOSLVL is given by:
VV
R
R+
LOSLVL
CC
LOSLVL
=
13
28
.
where voltages are in volts and resistances are in k
.
The smaller the external resistor, which implies a smaller
voltage difference from LOSLVL to VCC, the lower the LOS
sensitivity. Hence, larger input amplitude is required to
deassert LOS. The “Typical Operating Characteristics”
section contains graphs showing the relationship between
the input amplitude detection sensitivity and VLOSLVL or
RLOSLVL.
Hysteresis
The SY88973V provides typically 4.6dB LOS electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
the ratios change linearly as well. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88973V provides typically 2.3dB
LOS optical hysteresis. As the SY88973V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 4.6dB LOS hysteresis, a voltage factor of 1.7 is required
to deassert LOS.
Hysteresis and Sensitivity Improvement
If increased LOS sensitivity and hysteresis are required,
an application note entitled “Notes on Sensitivity and
Hysteresis in Micrel Post Amplifiers” is available at http://
www.micrel.com/product-info/app_hints+notes.shtml.
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