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參數(shù)資料
| 型號： | SY100EL35 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | JK Flip-Flop(JK觸發(fā)器) |
| 中文描述： | JK觸發(fā)器（JK觸發(fā)器） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 47K |
| 代理商： | SY100EL35 |
DESCRIPTION
FEATURES
JK FLIP-FLOP
PIN CONFIGURATION/BLOCK DIAGRAM
J
K
R
CLK
Qn+1
L
L
L
Z
Qn
L
H
L
Z
L
H
L
L
Z
H
H
H
L
Z
Qn
X
X
H
X
L
NOTE:
1. Z = LOW-to-HIGH transition.
SOIC
TOP VIEW
1
2
3
4
5
6
7
8
J
V
CC
Q
V
EE
K
R
Q
R
CLK
J
K
Rev.: E
Issue Date:
Amendment: /0
August, 1998
SY10EL35
SY100EL35
TRUTH TABLE
(1)
I
525ps propagation delay
I
2.2GHz toggle frequency
I
High bandwidth output transistions
I
Internal 75K
input pull-down resistors
I
Available in 8-pin SOIC package
The SY10/100EL35 are high-speed JK Flip-Flops. The
J/K data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave and,
thus, the outputs, upon a positive transition of the clock.
The reset pin is asynchronous and is activated with a
logic HIGH.
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY10EL52ZCTR | DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP |
| SY10EL52 | Differential Data and Clock D Flip-Flop(差分?jǐn)?shù)據(jù)時鐘D觸發(fā)器) |
| SY100EL52ZCTR | DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP |
| SY10EL57ZC | 4:1 DIFFERENTIAL MULTIPLEXER |
| SY100EL57ZC | 4:1 DIFFERENTIAL MULTIPLEXER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100EL35LZC | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:JK FLIP-FLOP |
| SY100EL35LZCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:JK FLIP-FLOP |
| SY100EL35LZG | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:JK FLIP-FLOP |
| SY100EL35LZGTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:JK FLIP-FLOP |
| SY100EL35LZI | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:JK FLIP-FLOP |
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