CC = +3.3V, V
參數(shù)資料
型號: SY100E310LJI
廠商: Micrel Inc
文件頁數(shù): 4/6頁
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:8 28-PLCC
標準包裝: 38
系列: 100E
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/是
輸入: LVECL,LVPECL
輸出: LVECL,LVPECL
頻率 - 最大: 800MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 管件
4
SY100E310L
Micrel, Inc.
M9999-072106
hbwhelp@micrel.com or (408) 955-1690
V
CC = +3.3V, VEE = 0V; TA = –40°C to +85°C; unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output High Voltage
R
L = 50 to VCC –2V
–1085
–955
–880
mV
(Q0-Q7, /Q0-/Q7)
V
OL
Output Low Voltage
R
L = 50 to VCC –2V
–1830
–1705
–1620
mV
(Q0-Q7, /Q0-/Q7)
V
IH
Input High Voltage
–1165
–880
mV
(CLKA, /CLKA, CLKB, /CLKB, CLK_SEL)
V
IL
Input Low Voltage
–1810
–1475
mV
(CLKA, /CLKA, CLKB, /CLKB, CLK_SEL)
V
IHCMR
Input High Voltage Common
Note 9
–1.5
–0.4
V
Mode Range (Differential)
(CLKA, / CLKA, CLKB, /CLKB)
V
BB
Output Reference Voltage
–1.38
–1.26
V
I
IN
Input HIGH Current
150
A
(CLKA, /CLKA, CLKB,/CLKB, CLK_SEL)
I
IL
Input LOW Current
0.5
A
(CLKA, /CLKA, CLKB, /CLKB, CLK_SEL)
LVNECL DC ELECTRICAL CHARACTERISTICS(7, 8)
V
CC = +3.0 to +3.6V and VEE = 0V or VCC = 0V and VEE = –3.0 to –3.6V; TA = –40°C to +85°C; unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
V
OUT = 400mV
800
MHz
tPD
Propagation Delay
Note 10
525
725
ps
CLKA-to-Q, CLKB-to-Q (Differential)
CLKA-to-Q, CLKB-to-Q (Single-ended)
Note 11
500
750
ps
tSKEW
Within-Device Skew
Note 12
50
ps
Part-to-Part Skew (Differential)
200
ps
tJITTER
Cycle-to-Cycle Jitter
1ps
RMS
VPP
Input Swing
Note 13
500
1000
mV
tr, tf
Rise / Fall Time (20% to 80%)
160
375
600
ps
(Q0-Q7, /Q0-/Q7)
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
8. Input and output parameters vary 1:1 with V
CC. VCC can vary ±0.3V.
9. V
IHCMR is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and then greater than or equal to V
PP(min).
10. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
11. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
12. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
13. V
PP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for
the E310L as a differential input as low as 50 mV will still produce full ECL levels at the output.
AC ELECTRICAL CHARACTERISTICS
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