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參數(shù)資料
| 型號(hào)： | SY100E256JZTR |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-BIT 4:1 MUX-LATCH |
| 中文描述： | 100E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 70K |
| 代理商： | SY100E256JZTR |
1
SY10E256
SY10E256
SY100E256
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
I
950ps max. data to output
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
850ps max. latch enable to output
I
Separate select controls
I
Differential outputs
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E256
I
Available in 28-pin PLCC package
FEATURES
3-BIT 4:1
MUX-LATCH
The SY10/100E256 offer three 4:1 multiplexers followed
by latches with differential outputs designed for use in new,
high-performance ECL systems. Separate Select controls
are provided for the leading 2:1 mux pairs (see block
diagram).
When the Latch Enable (LEN) is at a logic LOW, the latch
is transparent and output data is controlled by the multiplexer
select controls. A logic HIGH on LEN latches the outputs.
The Master Reset (MR) overrides all other controls to set
the Q outputs LOW.
DESCRIPTION
BLOCK DIAGRAM
Pin
Function
D
0x
–D
2x
Parallel Data Inputs
SEL
1A
, SEL
1B
First-stage Select Inputs
SEL
2
Second-stage Select Input
LEN
Latch Enable
MR
Master Reset
Q
0
, Q
0
–Q
2
, Q
2
Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
D
E
N
R
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
D
R
E
N
D
R
E
N
D
0a
D
0b
D
0c
D
0d
SEL
1B
D
1a
D
1b
D
1c
D
1d
D
2a
D
2b
D
2c
D
2d
SEL
1A
SEL
2
LEN
MR
Rev.: G
Issue Date:
Amendment: /0
March 2006
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