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參數(shù)資料
| 型號： | SY100E212JZ |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTER 3BIT SCAN 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 系列： | 100E |
| 邏輯類型： | 可掃描寄存器 |
| 電源電壓： | 4.2 V ~ 5.5 V |
| 位數(shù)： | 3 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 管件 |
Micrel, Inc.
SY58606U
November 2011
2
M9999-110411-D
hbwhelp@micrel.com
Ordering Information
(1)
Part Number
Package Type
Operating Range
Package Marking
SY58606UMG
QFN-16
Pb-Free
Industrial
606U with Pb-Free
bar-line indicator
SY58606UMGTR
(2)
QFN-16
Pb-Free
Industrial
606U with Pb-Free
bar-line indicator
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
All devices are Pb-Free.
2.
Tape and Reel.
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of this
pair internally terminates with 50 to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output
by latching the output to its last valid state. See “Input Interface Applications” subsection.
2
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to VT
pin. This pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” subsection.
3
VREF-AC
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection.
5, 8,13, 16
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the
VCC pins as possible.
6, 7, 14, 15
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same potential as
the ground pins.
9, 10
11, 12
/Q1, Q1
/Q0, Q0
CML Differential Output Pairs: Differential buffered copies of the input signal. The output
swing is typically 400mV. Unused output pair may be left floating with no impact on jitter.
See “CML Output Termination” subsection.
or (408) 955-1690
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| SY100E212JZ TR | 功能描述:IC REGISTER 3BIT SCAN 28-PLCC RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100E 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SY100E212JZTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTER |
| SY100E222L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 1.5GHz ±1/±2 DIFFERENTIAL LVECL/LVPECL PROGRAMMABLE CLOCK GENERATOR AND 1:15 FANOUT BUFFER |
| SY100E222L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 1.5GHz ±1/±2 DIFFERENTIAL LVECL/LVPECL PROGRAMMABLE CLOCK GENERATOR AND 1:15 FANOUT BUFFER |
| SY100E222L_11 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, 1.5GHz ?·1/?·2 DIFFERENTIAL LVECL/LVPECL PROGRAMMABLE CLOCK |
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