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參數(shù)資料
| 型號： | SY100E195JY TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 128TAP 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 100E, Precision Edge® |
| 標(biāo)片/步級數(shù)： | 128 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 1.39ns |
| 接頭增量： | 20ps |
| 可用的總延遲： | 1.39ns ~ 3.63ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | -4.2 V ~ -5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SY100E195JYTR SY100E195JYTR-ND |
5
Precison Edge
SY10E195
SY100E195
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
TA = 0
°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max. Unit
Condition
tPD
Propagation Delay to Output
ps
—
IN to Q; Tap = 0
1210
1360
1510
1240
1390
1540
1440
1590
1765
IN to Q; Tap = 127
3320
3570
3820
3380
3630
3880
3920
4270
4720
EN to Q; Tap = 0
1250
1450
1650
1275
1475
1675
1350
1650
1950
D7 to CASCADE
300
450
700
300
450
700
300
450
700
tRANGE
Programmable Range
2000
2175
—
2050
2240
—
2375
2580
—
ps
—
tPD (max.) – tPD (min.)
t
Step Delay
ps
6
D0 High
—
17
—
17.5
—
21
—
D1 High
—
34
—
35
—
42
—
D2 High
55
68
105
55
70
105
65
84
120
D3 High
115
136
180
115
140
180
140
168
205
D4 High
250
272
325
250
280
325
305
336
380
D5 High
505
544
620
515
560
620
672
740
D6 High
1000
1088
1190
1030
1120
1220
1240
1344
1450
Lin
Linearity
D1
D0
—D1
D0
—D1
D0
——
7
tskew
Duty Cycle Skew, tPHL–tPLH
—
±30
—
±30
—
±30
—
ps
1
tS
Set-up Time
ps
D to LEN
200
0
—
200
0
—
200
0
—
D to IN
800
—
800
—
800
—
2
EN to IN
200
—
200
—
200
—
3
tH
Hold Time
ps
LEN to D
500
250
—
500
250
—
500
250
—
IN to EN
0
—
0
—
0
—
4
tR
Release Time
ps
EN to IN
300
—
300
—
300
—
5
SET MAX to LEN
800
—
800
—
800
—
SET MIN to LEN
800
—
800
—
800
—
tjit
Jitter
—
<5
—
<5
—
<5
—
ps
8
tr
Rise/Fall Times
ps
—
tf
20–80% (Q)
125
225
325
125
225
325
125
225
325
20–80% (CASCADE)
300
450
650
300
450
650
300
450
650
Notes:
2. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
3. This set-up time defines the amount of time prior to the input signal the delay tap of the device must be set.
4. This set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75mV to
that IN/IN transition.
5. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than
±75mV to that IN/IN transition.
6. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified
IN to Q propagation delay and transition times.
7. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay
control inputs will typically realize D0 resolution steps across the specified programmable range.
8. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing
binary counts on the control inputs Dn). Typically, the device will be monotonic to the D0 input, however, under worst case conditions and process variation,
delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB, the device is guaranteed to be
9. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
VEE = VEE (Min.) to VEE (Max.); VCC = GND
AC ELECTRICAL CHARACTERISTICS
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