參數(shù)資料
型號(hào): SY100E016JY
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 8-BIT SYNCHRONOUS BINARY UP COUNTER
中文描述: 100E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 103K
代理商: SY100E016JY
4
SY10E016
SY100E016
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= –40
°
C
Min.
Typ. Max. Min.
T
A
= 0
°
C
Typ.
T
A
= +25
°
C
Typ. Max. Min.
T
A
= +85
°
C
Typ. Max.
Symbol
Parameter
Max. Min.
Unit
μ
A
mA
I
IH
Input HIGH Current
150
150
150
150
I
EE
Power Supply Current
10E
100E
151
151
181
181
151
151
181
181
151
151
181
181
151
174
181
208
TRUTH TABLE
(1)
CE
PE
TCLD
MR
CLK
Function
X
L
X
L
Z
Load Parallel (P
n
to Q
n
)
L
H
L
L
Z
Continuous Count
L
H
H
L
Z
Count; Load Parallel on TC = LOW
H
H
X
L
Z
Hold
X
X
X
L
ZZ
Master respond, Slaves Hold
X
X
X
H
Z
Reset (Q
n
: = LOW, TC : = HIGH)
NOTE:
1. Z = Clock Pulse (LOW-to-HIGH), ZZ = Clock Pulse (HIGH-to-LOW)
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= –40
°
C
Min.
Typ. Max.
T
A
= 0
°
C
Min.
T
A
= 25
°
C
Min.
T
A
= +85
°
C
Typ. Max.
Symbol
Parameter
Typ.
Max.
Typ. Max. Min.
Unit
f
COUNT
Max. Count Frequency
700
900
700
900
700
900
700
900
MHz
t
PD
Propagation Delay to Output
CLK to Q
MR to Q
CLK to TC (Qs loaded)
(1)
CLK to TC (Qs unloaded)
(1)
MR to TC
ps
600
600
550
550
625
725
775
775
700
775
1000
1000
1050
900
1000
600
600
550
550
625
725
775
775
700
775
1000
1000
1050
900
1000
600
600
550
550
625
725
775
775
700
775
1000
1000
1050
900
1000
600
600
550
550
625
725
775
775
700
775
1000
1000
1050
900
1000
t
S
Set-up Time
Pn
CE
PE
TCLD
ps
150
600
600
500
–30
400
400
300
150
600
600
500
–30
400
400
300
150
600
600
500
–30
400
400
300
150
600
600
500
–30
400
400
300
t
H
Hold Time
Pn
CE
PE
TCLD
ps
250
0
0
100
30
250
0
0
100
30
250
0
0
100
30
250
0
0
100
30
–400
–400
–300
–400
–400
–300
–400
–400
–300
–400
–400
–300
t
RR
Reset Recovery Time
900
700
900
700
900
700
900
700
ps
t
WP
Minimum Pulse Width
CLK, MR
400
400
400
400
ps
t
r
t
f
Rise/Fall Times
20% to 80%
300
510
800
300
510
800
300
510
800
300
510
800
ps
NOTE:
1. CLK to TC propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded, the noise generated in going from a IIII IIII
state to a 0000 0000 state causes the CLk to TC+ delay to increase.
AC ELECTRICAL CHARACTERISTICS
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